Hot-Carrier Degradation in Power LDMOS: Selective LOCOS-Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress

Breakdown-Voltage Degradation Under AC Stress of Thick SiO2 Capacitors for Galvanic Insulation

High-voltage dielectric breakdown of thick amorphous silicon-dioxide capacitors for galvanic insulation have been recently investigated showing a significant difference under dc and ac stresses. The impact-ionization generation is expected to be the dominant mechanism for thicknesses from about 1 to 15 mu m. Significant degradation of the breakdown voltage is observed for ac stress, which requires a focused TCAD-based investigation to fully understand the involved physical mechanisms. Accurate TCAD predictions of the measured leakage current allow us to validate the proposed model gaining a detailed understanding of the device breakdown regime

Boosting Static and Dynamic Performance of Integrated Solid-State Diodes By Peripheral Integration of Nanostructured Porous Silicon

Over the past two decades, different nanomaterials have been proposed for the design of novel silicon-based electronic devices or to push the performance of existing ones, leveraging the unique properties of charge carriers traveling in meso-to-nano scale structures. Porous silicon (PSi) is the nano- (n-PSi) to micro- (m-Psi) structured form of silicon achieved by anodic etching of a silicon wafer in acidic HF-based electrolytes. However, the low mobility and reduced lifetime of charge carriers traveling in n-PSi have been mainly perceived such as a deterioration the bulk silicon properties, thus hampering the use of n-PSi in micro and nano electronics to date. Here, we show that the integration of n-PSi in specific regions of a solid-state diode significantly improves both static and dynamic electrical performance of the diode, with respect to the unmodified device. Specifically, leveraging the unique mobility and lifetime of charge carriers traveling in the n-PSi layer, we achieve a significant increase of the breakdown voltage (>2x) and reduction of the turn-off time (about 30%). This improvement is shown to be robust with respect to n-PSi preparation conditions and diode typologies. Two dimensional (2D) TCAD simulations further corroborate that the improvement of the electrical performance of n-PSi modified diodes is related to the strong mobility and lifetime reduction of carriers in the nanostructured porous silicon layer. Remarkably, no significant drawbacks are observed after the peripheral integration of n-PSi in solid-state diodes, thus confirming the beneficial effect of n-PSi when employed for the modification of micro and nano electronic devices. A. Paghi, L. M. Strambini, F. F. Toia, M. Sambi, M. Marchesi, R. Depetro, M. Morelli, G. Barillaro, Peripheral Nanostructured Porous Silicon Boosts Static and Dynamic Performance Of Integrated Electronic Devices, Advanced Electronic Materials 6, 2000615 (2020)

AN ELECTRONIC JUNCTION DEVICE WITH A REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT RECIRCULATION PHENOMENON AND RELATED MANUFACTURING PROCESS

An integrated electronic device having a semiconductor body (30) including: a first electrode region (32) having a first type of conductivity; and a second electrode region (28, 34, 38) having a second type of conductivity, which forms a junction with the first electrode region. The integrated electronic device further includes a nanostructured semiconductor region (48), which extends in one of the first and second electrode regions (32; 28, 34, 38)

Hot-carrier degradation in power LDMOS: Drain bias dependence and lifetime evaluation

In this brief, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOSFET (LDMOS) transistors. When a relatively high drain voltage is applied during the ON-state regime, high energetic and/or multiple cold electrons are recognized as the main source of degradation affecting the LDMOS lifetime: The latter is usually extrapolated at typical operating drain voltages. Hence, the extrapolation criterion is particularly critical, and different models have been proposed in the past and discussed in this brief. In particular, the dependence of ON-resistance degradation (RON) on drain bias is investigated, and a simplified extrapolation model, accounting for the saturation effects of RON at long stress times, is proposed and validated by comparison with experiments and advanced physics-based TCAD simulations, confirming the ability to accurately estimate lifetime on devices featuring short-circuited source-body contacts