ELECTRICAL CHARACTERIZATION OF THE FORWARD CURRENTVOLTAGE OF AL IMPLANTED 4H-SIC PIN DIODES

ABSTRACTIn this work,theforward current-voltagecharacteristics of n-type Al implanted 4H-SiC pin diodeshave been investigatedexperimentally and by mean of numerical simulations in the 298-378K temperature range. Our simulations were performedusing proprietary simulations software. The model parameters to be calibrated in the simulation are the electron and holeminority carriers lifetimes.The measured forward I-V characteristics showed two differentbehaviour, the leaky behaved andwell behaved diode. The later diodes were considered for simulation comparison.Employing temperature-dependent carrierlifetimes as a fitting parameter, the simulation indicates that drift layer and bulk carrier lifetime ranging from 10ns to 50ns. Weachieved a good agreement between simulations and measured data. The measured and the simulated forward characteristicsindicate an ideality factor of about1.3for the region 2.5V-2.78Vand 2.14 in the low injection region. Activation energies ofabout 1.61eV and 2.51eVare obtained respectively which are in good agreement with the expected values.KEYWORDS: p-i-n diode, silicon carbide, silvaco, device simulation, lifetimes

Radiation Hardness Studies in a CCD with High-Speed Column Parallel Readout

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) collaboration is developing Column-Parallel CCDs (CPCCDs) for the vertex detector of the International Linear Collider (ILC). The CPCCDs can be read out many times faster than standard CCDs, significantly increasing their operating speed. The results of detailed simulations of the charge transfer inefficiency (CTI) of a prototype CPCCD are reported and studies of the influence of gate voltage on the CTI described. The effects of bulk radiation damage on the CTI of a CPCCD are studied by simulating the effects of two electron trap levels, 0.17 and 0.44 eV, at different concentrations and operating temperatures. The dependence of the CTI on different occupancy levels (percentage of hit pixels) and readout frequencies is also studied. The optimal operating temperature for the CPCCD, where the effects of the charge trapping are at a minimum, is found to be about 230 K for the range of readout speeds proposed for the ILC. The results of the full simulation have been compared with a simple analytic model.Comment: 3 pages, 6 figures; presented at IEEE'07, ALCPG'07, ICATPP'0

Analysis of 4H-SiC MOSFET with distinct high-k/4H-SiC interfaces under high temperature and carrier-trapping conditions

In this work, the reliability of different oxide/4H-SiC interfaces under high temperature and carrier-trapping conditions are investigated carefully. In more detail, the carrier-trapping and temperature effects are considered in the electrical characterization of a low breakdown 4H-SiC-based MOSFET by using in turn SiO2, Si3N4, AlN, Al2O3, Y2O3 and HfO2 as gate dielectric. A gate oxide with a high relative permittivity notably improves the transistor performance. In addition, HfO2 assures the MOSFET best immunity behaviors. The obtained results are explained in terms of the carrier channel mobility, device on-state resistance, and oxide electric field. By using HfO2, however, an increased gate leakage current is calculated. This drawback is overcome by inserting a thin interfacial layer (2 nm-thick) in the HfO2/4H-SiC MOS structure. In particular, two alternative gate stacked dielectrics, involving either SiO2 or Al2O3, have proven their effectiveness in preserving the transistor on-state figures of merit while limiting the gate leakage current in the whole explored gate voltage range. To support the prediction capabilities of the presented modeling analysis, the simulations results are compared with experimental data from literature resulting in a good agreement. Low power MOSFETs are used in several applications for which reliability and durability are as critical as performance. For example, referring to power optimizers for photovoltaic (PV) modules, which fall under the low-load and low-voltage category of DC–DC converters, these devices significantly increase the energy generated by each single PV module operating under harsh conditions and stressing environments. In addition, they have to ensure high reliability over the long term of operation

MEASUREMENT AND ANALYSIS OF I-V-T CHARACTERISTICS OF A AUGENI/P-SI SCHOTTKY BARRIER DIODE

ABSTRACTIn this work, we report measured forward current voltage characteristics of AuGeNi/p-Si schottky barrier diode in thetemperature range of 295-400 °K. Forward current voltage characteristics were investigated. This investigation is based on theanalysis of the dependency of extracted parameters such as ideality factor (η), barrier height ( ) and saturation current ( )on temperature. The Richardson coefficient was examined by means of the saturation versus temperature. While η decreases,ØB0 increases with increasing temperature. Obtained Richardson constant value of the A*=11.5 x10-7Acm-2K-2 is very lowcompared to the standard value. The modified Richardson plot has given mean barrier height and Richardson constant(A*) as 1.15 eV and 30.53 Am-2K-2, respectively. The temperature dependence of the I–V characteristics of the AuGeNi/p-SiSchottky diode have been successfully explained on the basis of thermionic emission (TE) mechanism with Gaussiandistribution of the Schottky barrier heights (SBHs).KEYWORDS: Schottky contacts, current-voltage-temperature characteristics, Gaussian distribution, Barrier inhomogeneity

Improving the efficiency of a-Si:H/c-Si thin heterojunction solar cells by using both antireflection coating engineering and diffraction grating

In this paper, we present an analytical study of the impact of light trapping and multilayer antireflection coating (ARC) on the electrical characteristics of n(a-Si:H)/i(a-Si:H)/p(c-Si)/p+(C-Si) heterojunction solar cells with intrinsic thin layer (SHJ). The developed analytical model considers a triangular texture morphology of the solar cell top surface and a double ARC layer. This model serves as a fitness function to optimize the device reliability against the interfacial traps using Grey Wolf optimization approach (GWO). The optimized solar cell reveals a high short circuit current I SC = 47.9 mA, an open circuit voltage V OC = 0.56 V, fill factor FF = 74.72% and a conversion efficiency improvement in the order of 30% over conventional planar solar cells efficiency. Not only the optimized SHJ solar cell exhibits higher performance in terms of figure of merits, but also shows superior interfacial traps reliability at the amorphous/crystalline interface. This reliability enhancement is due to a better surface texture control and intrinsic thin film layer tuning provided by GWO approach

Temperature and SiO2/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs

The temperature and carrier-trapping effects on the electrical characteristics of a 4H silicon carbide (4H-SiC) metal–oxide–semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BVDS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects-free). In particular, the threshold voltage (Vth), channel mobility (µch), and on-state resistance (RON) are calculated in the temperature range of 300 K to 500 K starting from the device current–voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H-SiC bandgap (deep and tail centers) and oxide-fixed traps is taken into account referring to literature data. The simulation results show that the SiO2/4H-SiC interface traps act to increase RON, reduce µch, and increase the sensitivity of Vth with temperature. In more detail, the deep-level traps in the mid-gap have a limited effect in determining RON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2Vth (i.e., VGS > 12 V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the RON increase in particular at low temperatures. Finally, a high oxide-fixed trap density meaningfully influences Vth (negative shifting) and penalizes the device drain current over the whole explored voltage range

Analysis of the Forward I–V Characteristics of Al-Implanted 4H-SiC p-i-n Diodes with Modeling of Recombination and Trapping Effects Due to Intrinsic and Doping-Induced Defect States

In this paper, the impact of silicon carbide intrinsic defect states, such as Z1/2 and EH6/7 centers, on the forward current–voltage curves of aluminum (Al)-implanted 4H-SiC p-i-n diodes is investigated by means of a physics-based device simulator. During the simulations, an explicit carrier trap effect due to an electrically active defect concentration produced by the Al+ ion implantation process in the anode region was also taken into account. The obtained current–voltage characteristics are compared with those measured experimentally for several samples at different current levels. It is found that intrinsic defect densities as high as the epilayer doping may lead to undesirable device properties and instability of the forward bias behavior. The diode ideality factor and the series resistance increase with the increase of defects and could be controlled by using high-purity epi-wafers. Furthermore, due to their location in the bandgap and capture cross-sections, the impact of Z1/2 centers on the device electrical characteristics is more severe than that of EH6/7 centers

Investigation of dry reforming of methane over Mo-based catalysts

An investigation of methane dry reforming over Mo–Ni based catalysts is carried out in a fixed bed catalytic reactor at different temperatures. Two Mo–Ni catalysts supported on alumina are prepared with 20%Mo–10%Ni and 20%Mo–2%Ni, respectively, in which the nickel is used for its highly resistance at high temperature during dry reforming of methane (DRM) reaction. Experimental results shows that an increase in temperature favours the CH4 conversion and determined a higher H2/CO ratio. A small amount of deposited coke is observed because of the abundant presence of CO2 in the reaction medium and only for 2% Ni catalysts. A kinetic model is proposed for the DRM with Mo–Ni based catalysts, in which the reaction mechanism routes and the operating conditions such as the reaction temperature and the CH4/CO2 molar ratio are accounted for. The results of the mathematical model allow a consistent description of the experimental data, in terms of gas outlet composition. The absence of the methane decomposition reaction, responsible of carbon deposition that is known to lead to catalyst deactivation, is the main result that is adequately predicted by the model