35 research outputs found

    RoCoCo: row and column compression for high-performance multiplication on FPGAs

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    Due to copyright restrictions, the access to the full text of this article is only available via subscription.Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool

    RoCoCo: row and column compression for high-performance multiplication on FPGAs

    No full text
    Due to copyright restrictions, the access to the full text of this article is only available via subscription.Multiplication is, in no doubt, one of the top few frequently used operations in hardware and software. In high-performance hardware design, after high-level optimizations are exhausted, component level optimizations are employed such as building fast multipliers. Most fast multiplier architectures use some form of a Carry Save Adder (CSA) Tree, which is also called Column Compression (CC). We propose a new CC method called RoCoCo (Row and Column Compression), which also compresses the tree along rows so that the final adder is small and fast. Although CC results in faster multipliers in ASIC implementations, it is an assumption by designers that they are not the wisest choice on FPGAs. On the contrary, we were able to show through Xilinx synthesis results that RoCoCo (and sometimes Dadda CC) frequently offer faster multipliers than the built-in implementation of the multiply operation in Xilinx ISE synthesis tool

    İlköğretim Birinci Sınıf Öğrencilerinin Teknoloji Kullanım Sıklığı ve Ebeveyn Görüşleri

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    Giriş: Teknolojide yaşanan hızlı gelişmeler, her alanda olduğu gibi eğitim alanında da kendini göstermiştir. Yapılan çalışmalarda, teknolojinin etkili ve amacına uygun olarak kullanıldığı takdirde çocuklar üzerinde olumlu, gereğinden fazla kullanıldığında ise pek çok olumsuz etki yarattığı ortaya çıkmıştır. Bu çalışma ise, ilköğretim birinci sınıf öğrencilerinin teknoloji kullanım sıklıklarını ve ebeveyn görüşlerini incelemek amacı ile yapılmıştır. Gereç- Yöntem: Tanımlayıcı nitelikteki bu çalışmanın evrenini (n:240) İstanbul ilinde bir ilkokulun tüm birinci sınıf öğrencilerinin ebeveynleri oluşturmuştur. Örneklemi ise araştırmaya katılmayı kabul eden 151 sayıda veliden oluşmuştur. Uzman görüşleri ile araştırmacılar tarafından hazırlanan üç bölümden oluşan bir ölçek kullanılmıştır. Araştırmada veri toplama aracı olarak kullanılan anket, Likert ölçeği şeklinde hazırlanmıştır. Bulgular: Araştırmaya katılan ebeveynlerin 100’ü (%66,2) telefon, 41’i (%27,2) tablet ile çocukların internete giriş yaptığını belirtmiştir. Katılımcıların %67,5’i bilgisayar ve internet bağlantısına sahip olduğunu ifade etmiştir. Ebeveynlerin internet hakkındaki kısaca düşünceleri incelendiğinde, katılımcıların 94’ü (%62,7) internet erişimi için olmalı cevabını vermişlerdir. Sonuç: Çocukların güvenli bir şekilde teknolojiyi kullanmaları adına en önemli denetleyicilerden biri olan ebeveynlerin bu konuda farkındalıklarını arttırmaya yönelik çalışmalara önem verilmelidir. Bu bağlamda devlet kurumları, belediyeler, aile sağlığı merkezleri, sivil toplum örgütleri tarafından özellikle bilgisayar-internet gibi teknoloji ürünlerinin çocukların sağlığı üzerindeki etkilerine karşı güvenli kullanım önerileri sunmak amacıyla eğitim faaliyetleri düzenlenebilir

    Is medial calcar continuity necessary in plate osteosynthesis for proximal humerus fractures?

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    WOS: 000427371000018PubMed: 29519987Objective: To evaluate the functional and radiological results of patients with and without medial calcar continuity in plate osteosynthesis applied for a proximal humerus fracture retrospectively. Methods: The study included 27 patients to whom plate osteosynthesis was applied because of a proximal humerus fracture between January 2, 2010, and December 30, 2013, at Okmeydani Research and Training Hospital. Patients were separated into Group A with medial calcar continuity and Group B without medial calcar continuity. On the radiographs taken postoperatively and at the final follow-up examination, measurements were taken of the humeral head height and the humeral neck-shaft angle. The presence of avascular necrosis was recorded. Results: The functional and radiological results of the patients were evaluated after a mean follow-up of 39.1 months. No statistically significant difference was determined between Groups A and B in respect of the postoperative and the final follow-up humeral head height (P > 0.05). No statistically significant difference was determined between Groups A and B in respect of the postoperative and the final follow-up humeral neck-shaft angle (P > 0.05). Plate breakage was seen in one patient without medial calcar continuity. Penetration of the screw into the joint was determined in one patient in Group A and three patients in Group B. No avascular necrosis or infection was seen in any patient. Conclusion: When the surgical process has not damaged the soft tissue and sufficient stability has been achieved, providing calcar continuity is not an absolute condition

    Design of a modular wideband high voltage reference divider

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    This paper describes the design of a modular high voltage divider for calibration purposes. The frequency response of the modular divider is flat from DC up to c. 10 MHz. The 100 kV modules can be stacked to reach higher voltages. The divider is mainly targeted for on-site calibration of DC, AC and impulse voltage measuring systems in high voltage testing laboratories. It can also be used for precision measurement of combined and composite voltage test waveforms
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