Generalized complex structure on certain principal torus bundles

A principal torus bundle over a complex manifold with even dimensional fiber and characteristic class of type $(1,1)$ admits a family of generalized complex structures. We show that such a generalized complex structure is equivalent to the product of the complex structure on the base and the symplectic structure on the fiber in a tubular neighborhood of the fiber. This has consequences for the generalized Dolbeault cohomology of the bundle.Comment: 19 page

Zoom Out and See Better: Scalable Message Tracing for Post-Silicon SoC Debug

We present a method for selecting trace messages for post-silicon validation of System-on-Chip (SoC). Our message selection is guided by specifications of interacting flows in common user applications. In current practice, such messages are selected based on designer expertise. We formulate the problem as an optimization of mutual information gain and trace buffer utilization. Our approach scales to systems far beyond the capacity of current signal selection techniques. We achieve an average trace buffer utilization of 98.96% with an average flow specification coverage of 94.3% and an average bug localization to only 21.11% of the potential root causes in our large-scale debugging effort. We present efficacy of our selected messages in debugging and root cause analysis using five realistic case studies consisting of complex and subtle bugs from the OpenSPARC T2 processor.IBMOpe

SCAR: Power Side-Channel Analysis at RTL-Level

Power side-channel attacks exploit the dynamic power consumption of cryptographic operations to leak sensitive information of encryption hardware. Therefore, it is necessary to conduct power side-channel analysis for assessing the susceptibility of cryptographic systems and mitigating potential risks. Existing power side-channel analysis primarily focuses on post-silicon implementations, which are inflexible in addressing design flaws, leading to costly and time-consuming post-fabrication design re-spins. Hence, pre-silicon power side-channel analysis is required for early detection of vulnerabilities to improve design robustness. In this paper, we introduce SCAR, a novel pre-silicon power side-channel analysis framework based on Graph Neural Networks (GNN). SCAR converts register-transfer level (RTL) designs of encryption hardware into control-data flow graphs and use that to detect the design modules susceptible to side-channel leakage. Furthermore, we incorporate a deep learning-based explainer in SCAR to generate quantifiable and human-accessible explanation of our detection and localization decisions. We have also developed a fortification component as a part of SCAR that uses large-language models (LLM) to automatically generate and insert additional design code at the localized zone to shore up the side-channel leakage. When evaluated on popular encryption algorithms like AES, RSA, and PRESENT, and postquantum cryptography algorithms like Saber and CRYSTALS-Kyber, SCAR, achieves up to 94.49% localization accuracy, 100% precision, and 90.48% recall. Additionally, through explainability analysis, SCAR reduces features for GNN model training by 57% while maintaining comparable accuracy. We believe that SCAR will transform the security-critical hardware design cycle, resulting in faster design closure at a reduced design cost

Utilization of Iron Ore Tailings for Brick Manufacture from Donimalai Mines of Karnataka, India

Mixing iron tailings with cement, sand and sodium silicate for manufacturing bricks was studied with the objective of converting the iron ore tailing waste into value-added products. Bricks were prepared using different compositions of iron tailings with proportions of Ordinary Portland Cement, sodium silicate and sand in cuboid mould (9″ X 5″X 3″). Bricks were air dried for 24 hours, placed in oven for 115 ± 10 °C for 24 hours. Mechanical properties such as compressive strength (CS), water absorption (WA), and efflorescence were measured. The maximum CS of 8.58 N/mm2 was recorded for tailing and cement ratios of 8:2. However, for making it more economical the ratio of 9:1 was considered and this compares very well with the Indian standard (IS): 3495 (Part 1) (1992) of bricks. The results also indicated that the tailing percentage in the bricks affects their mechanical properties. The WA rates of the manufactured bricks are low compared to standard fired clay bricks, and the same varies with process parameters. The low capillary pore may deter the formation of efflorescence. The process, with standardized parameters, may be commercially adapted, and large quantities of iron ore tailings may be put to use in making bricks. Thus, the process technology observed in this paper can potentially convert the huge amount of environmentally hazardous waste into value added product. Iron ore tailing may materialize as a sustainable supplement to soil's clay, use of which in brick making is restricted. The finding also usher a new area of research

Utilization of Iron Ore Tailings for Brick Manufacture from Donimalai Mines of Karnataka, India

210-220The iron tailings were mixed in various proportions with different combinations of cement, sand, and sodium silicate to obtain or value-added product out of iron tailing waste which is suitable for use in the construction industry. Bricks were made using a variety of compositions of iron tailings, Ordinary Portland Cement, sodium silicate, and sand in cuboid mould (9″X 5″X 3″). The bricks were dried for 24 hours, and then kilned at 115 ± 10°C for 24 hours. Mechanical features such as water absorption, compressive strength, and efflorescence are tested. The maximum compressive strength rating of 8.58 N/mm2 was recorded with ratios of 8:2 (Iron tailing and cement). However, in process of making it economical, the ratio of 9:1 has opted and this ratio complies with the requirement of the Indian standard (IS: 1077:1992) of the common burnt clay building bricks. Water absorption for the proposed bricks is less than that of burnt clay bricks. The lower capillary pore can prevent the formation of efflorescence. This process, with the same parameters, can be exchanged commercially, and a large number of wastes of iron ore can be used to make bricks. Therefore, the technological processes identified in this paper can convert large amounts of hazardous waste into the environment into value-added products. Iron tailing can be seen as a stable addition to clay soils, its use when restricted to making bricks. This research helps to open a new area of research

Scalable functional validation of next generation SoCs

System-on-Chips (SoCs) constitutes the primary backbone of modern embedded computing devices including many safety-critical applications e.g., autonomous vehicles, health care systems. The presence of any undetected bugs in these systems would have aberrant cost both in terms of safety and reliability and can cause loss of property or life. Hence, SoC validation is a crucial task to ensure the functional correctness of an SoC. The sheer size, presence of hundreds of concurrently executing heterogeneous IPs, vertical integration of SoC components e.g., hardware/firmware/software to realize multiple functionality, and application-level relevance of components present a new spectrum of validation challenges that have rendered the traditional microprocessor validation paradigm moot in the context of SoC validation. The challenges include observability enhancement and debug and diagnosis under the constraint of vertical integrations, identifying high-quality verification artifacts among others. In industrial practice, SoC validation is a manual, unsystematic, and ad hoc process that heavily relies on the expertise and the creativity of the validator. Consequently, there is an urgent need to develop scalable and efficient algorithms of industrial relevance to address this massive ongoing challenge of SoC validation. This dissertation makes contributions to both post-silicon and pre-silicon validation of SoCs, with highly impactful contributions to next-generation post-silicon SoC validation. We use top-down analysis, a higher level of abstraction, and application relevance as the key ideas to automate post-silicon observability enhancement for industrial scale SoCs and scale observability to design that is more than 300x the size of designs that have been presented in the academic literature so far. Our observability enhancement solution can be applied at the netlist-level, behavioral level, and at the system-wide application level to select high-quality signals that are most beneficial for post-silicon debug and diagnosis. We apply a feature engineering based machine learning technique on the observed signal data to develop an automatic, scalable, and efficient post-silicon debug and diagnosis solution. The key idea is to learn the correct and erroneous design behavior automatically from trace data without prior design knowledge. We believe our debugging solution can automate post-silicon debug and diagnosis, where manual debugging is the norm. The quality of SoC verification and validation heavily depends on the quality of verification artifacts e.g., assertions. To automate and expedite identification of high-functional coverage assertions that are useful for regression analysis, localization, etc., we have also developed a comprehensive ranking scheme for assertions. The key idea is to identify assertions that capture important design behaviors by analyzing the design source code. Our SoC validation solutions are scalable and efficient. We consistently show orders of magnitude speedup improvements over the state-of-the-art while objectively improving quality of results. We have shown that going forward application-level analysis is the key to scale post-silicon validation to industrial scale SoCs. Our proposed validation solutions can plug into the existing industrial validation process to introduce automation in the current unsystematic, ad hoc, manual settings with multiple order of magnitudes of benefit.U of I OnlyAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD syste

Diffusion-driven instability and pattern formation in a prey-predator model with fear and Allee effect

This paper analyses a predator-prey model with Holling type II response function incorporating Allee and fear effect in the prey. The model includes intra species competition among predators. We find out the local dynamics as well as Hopf bifurcation by considering level of fear as bifurcation parameter. The condition for diffusion-driven instability and patterns are then demonstrated in relation to the system's ecological parameters and diffusion coefficients. Intra-specific competition affects the dynamics of the system and Turing pattern formation. Moreover, output of results is verified through numerical simulation. Thus, from a dynamical standpoint, the considered model seems to be relevant in the field of ecology

A library for passive online verification of analog and mixed-signal circuits

The development and use of assertions in the Analog and Mixed-signal (AMS) domain is a subject which has attracted significant attention lately from the verification community. Recent studies have suggested that natural extensions of assertion languages (like PSL and SVA) into the AMS domain are not expressive enough to capture many AMS behaviors, and that a library of auxiliary AMS functions are needed along with the assertion language. The integration of auxiliary functions with the core fabric of a temporal logic is non-trivial and can be challenging for a verification engineer. In this paper we propose a purely library-based verification approach, where libraries for checking elementary properties can be naturally connected with libraries for auxiliary functions to monitor complex AMS behaviors. We study the modeling of behaviors with the proposed library, and outline the main challenges and their solutions towards implementing the verification library over commercial AMS simulators

Fabrication of CR: Yagdoped Silica Optical Fiber Using Modified Powder in Tube Technique

Fabrication of Cr-YAG doped silica optical fiber suitable for tunable laser source using a modified powder in tube technique is reported for the first time. Initial performance along with its optical and material characterization is also presented

Chassis: a platform for verifying pmu integration using autogenerated behavioral models

Power Management Units (PMUs) are large integrated circuits consisting of many predesigned mixed-signal components. PMU integration poses a serious verification problem considering the size of the integrated circuit and the complexity of analog simulation. In this article we present an approach for automatic generation of behavioral models for PMU components from top-down skeleton models, fitted with parameter values estimated by bottom-up parameter extraction algorithms. It is shown that replacing PMU components with these autogenerated hybrid automata-based abstract behavioral models enables significant simulation speedup (> 20X on our industrial test cases) and helps in early detection of integration errors. The article also justifies the level of accuracy in our models with respect to the goal of verifying integrated PMUs. The approach presented in this work is implemented in the form of a tool suite called Chassis