2011-2012 Dean\u27s Showcase

https://spiral.lynn.edu/conservatory_deansshowcase/1023/thumbnail.jp

A Vectorizing SUIF Compiler

With advances in VLSI technology, it is now possible to implement vector processors on a single chip. Vector architectures are ideal for providing the cost-effective, real-time performance demanded by graphicintensive applications such as MPEG players and video conferencing software. However, these vector microprocessors lack compilers and instead rely on libraries of hand-written assembly functions that use their vector hardware. For our research, we are developing a retargetable vectorizing compiler for such vector microprocessors to improve their ease of use. The starting point for our work is the SUIF compiler. In this paper, we describe how we augmented SUIF and discuss which aspects of SUIF were or were not needed for the retargeting effort. For example, we added code that uses SUIF's library of dependence tests to identify vectorizable loops. On the other hand, because of the mapping of high-level loop structures to vector instructions, we do not rely heavily on SUIF's scalar op..

A vectorizing SUIF compiler, implementation and performance

grantor: University of TorontoDesktop computers are increasingly used for DSP, multi-media, and data visualization applications. These codes contain a high degree of loop level parallelism, which cannot be fully exploited by superscalar processors. Vector architectures are a viable alternative for increasing workstation performance. Vector architectures require more compiler support to exploit the available parallelism in a program than superscalar architectures do. Development effort thus shifts from hardware to compiler design. This thesis describes the development of a vectorizing compiler, implemented in SUIF, capable of targeting a wide variety of vector architectures. The development of a code generator for the T0 vector-microprocessor is also discussed. Performance of T0-like vector processors on a set of multimedia and data-filter applications is also shown to demonstrate the effectiveness of the compiler and to show the applicability of vector architectures to multi-media applications and other common work loads.M.A.Sc

A Vectorizing SUIF Compiler

With advances in VLSI technology, it is now possible to implement vector processors on a single chip. Vector architectures are ideal for providing the cost-effective, real-time performance demanded by graphicintensive applications such as MPEG players and video conferencing software. However, these vector microprocessors lack compilers and instead rely on libraries of hand-written assembly functions that use their vector hardware. For our research, we are developing a retargetable vectorizing compiler for such vector microprocessors to improve their ease of use. The starting point for our work is the SUIF compiler. In this paper, we describe how we augmented SUIF and discuss which aspects of SUIF were or were not needed for the retargeting effort. For example, we added code that uses SUIF’s library of dependence tests to identify vectorizable loops. On the other hand, because of the mapping of high-level loop structures to vector instructions, we do not rely heavily on SUIF’s scalar optimizations to generate high quality vector code. To demonstrate the effectiveness of our SUIF vectorizing compiler, we show how it transforms an MPEG decoder program into vector assembly code. Over the last decade, computer technology has developed to the point where applications such as M-PEG players, video conferencing programs like the H.261 standard, 3D visualization software, and CAD tools are enjoyin

Observability-based Optimization of Coordinated Sampling Trajectories for Recursive Estimation of a Strong, Spatially Varying Flowfield

Autonomous vehicles are effective environmental sampling platforms whose sampling performance can be optimized by path-planning algorithms that drive vehicles to specific regions of the operational domain containing the most informative data. In this paper, we apply tools from nonlinear observability, nonlinear control, and Bayesian estimation to derive a multi-vehicle control algorithm that steers vehicles to an optimal sampling formation in an estimated flowfield. Sampling trajectories are optimized using the empirical observability gramian, which quantifies the sensitivity of output measurements to variations of the flowfield parameters. We reconstruct the parameters of the flowfield from noisy flow measurements collected along the sampling trajectories using a recursive Bayesian filter

Producer perceptions of manual and automated milk feeding systems for dairy calves in Canada

As part of a cross-sectional survey, Canadian dairy producers were asked a set of questions to: (1) determine factors that influenced them to continue using manual milk feeding (MMF) systems or to switch to automated milk feeders (AMF), and (2) investigate producersâ perceived advantages and disadvantages regarding both feeding systems. A total of 670 responses were received. Among respondents, 16% used AMF and 84% used MMF. The four most frequent factors that producers reported as important in motivating them to switch to AMF were to raise better calves, offer more milk to calves, reduce labor, and improve working conditions. For MMF farms, investment in equipment and group housing facilities, as well as farm size, were the primary reasons reported for their continued use of MMF systems. The principal perceived advantages of having an AMF were that calves are able to express natural behaviors and drink more milk without increased labor input. For MMF systems, the main perceived advantage was related to easier identification of sick calves. Results provide insights into factors affecting the choice of calf feeding methods by dairy producers, and improve understanding of producersâ needs and expectations regarding calf management and adoption of technology.The accepted manuscript in pdf format is listed with the files at the bottom of this page. The presentation of the authors' names and (or) special characters in the title of the manuscript may differ slightly between what is listed on this page and what is listed in the pdf file of the accepted manuscript; that in the pdf file of the accepted manuscript is what was submitted by the author

Exploiting Superword Level Parallelism with Multimedia Instruction Sets

Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general-purpose microprocessors. This added functionality comes primarily in the addition of short SIMD instructions. Unfortunately, access to these instructions is limited to in-line assembly and library calls. Some researchers have proposed using vector compilers as a means of exploiting multimedia instructions. Although vectorization technology is well understood, it is inherently complex and fragile. In addition, it is incapable of locating SIMD-style parallelism within a basic block. In this paper we introduce the concept of Superword Level Parallelism(SLP), a novel way of viewing parallelism in multimedia applications. We believe SLP is fundamentally different from the loop-level parallelism exploited by traditional vector processing, and therefore warrants a different method for extracting it. We have developed a simple and robust compiler technique for detecting SLP that targets basic blocks rather than loop nests. As with techniques designed to extract ILP, ours is able to exploit parallelism both across loop iterations and within basic blocks. The result is an algorithm that provides excellent performance in several application domains. Experiments on scientific and multimedia benchmarks have yielded average performance improvements of 84%, and range as high as 253%.