A Vectorizing SUIF Compiler

Abstract

With advances in VLSI technology, it is now possible to implement vector processors on a single chip. Vector architectures are ideal for providing the cost-effective, real-time performance demanded by graphicintensive applications such as MPEG players and video conferencing software. However, these vector microprocessors lack compilers and instead rely on libraries of hand-written assembly functions that use their vector hardware. For our research, we are developing a retargetable vectorizing compiler for such vector microprocessors to improve their ease of use. The starting point for our work is the SUIF compiler. In this paper, we describe how we augmented SUIF and discuss which aspects of SUIF were or were not needed for the retargeting effort. For example, we added code that uses SUIF's library of dependence tests to identify vectorizable loops. On the other hand, because of the mapping of high-level loop structures to vector instructions, we do not rely heavily on SUIF's scalar op..