Transparent and Flexible Graphene Charge-Trap Memory

A transparent and flexible graphene charge-trap memory (GCTM) composed of a single-layer graphene channel and a 3-dimensional gate stack was fabricated on a polyethylene naphtalate substrate below eutectic temperatures (∼110 °C). The GCTM exhibits memory functionality of ∼8.6 V memory window and 30% data retention per 10 years, while maintaining ∼80% of transparency in the visible wavelength. Under both tensile and compressive stress, the GCTM shows minimal effect on the program/erase states and the on-state current. This can be utilized for transparent and flexible electronics that require integration of logic, memory, and display on a single substrate with high transparency and endurance under flex

Graphene for True Ohmic Contact at Metal–Semiconductor Junctions

The rectifying Schottky characteristics of the metal–semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni–Si junction, one of the most commonly used metal–semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10^–8 ∼ 10^–9 Ω cm² at a Si doping concentration of 10¹⁷ cm^–3

Reliable Multivalued Conductance States in TaO_<i>x</i> Memristors through Oxygen Plasma-Assisted Electrode Deposition with in Situ-Biased Conductance State Transmission Electron Microscopy Analysis

Transition metal oxide-based memristors have widely been proposed for applications toward artificial synapses. In general, memristors have two or more electrically switchable stable resistance states that device researchers see as an analogue to the ion channels found in biological synapses. The mechanism behind resistive switching in metal oxides has been divided into electrochemical metallization models and valence change models. The stability of the resistance states in the memristor vary widely depending on: oxide material, electrode material, deposition conditions, film thickness, and programming conditions. So far, it has been extremely challenging to obtain reliable memristors with more than two stable multivalued states along with endurances greater than ∼1000 cycles for each of those states. Using an oxygen plasma-assisted sputter deposition method of noble metal electrodes, we found that the metal-oxide interface could be deposited with substantially lower interface roughness observable at the nanometer scale. This markedly improved device reliability and function, allowing for a demonstration of memristors with four completely distinct levels from ∼6 × 10^–6 to ∼4 × 10^–8 S that were tested up to 10⁴ cycles per level. Furthermore through a unique in situ transmission electron microscopy study, we were able to verify a redox reaction-type model to be dominant in our samples, leading to the higher degree of electrical state controllability. For solid-state synapse applications, the improvements to electrical properties will lead to simple device structures, with an overall power and area reduction of at least 1000 times when compared to SRAM