34 research outputs found
Formalizing Size-Optimal Sorting Networks: Extracting a Certified Proof Checker
Since the proof of the four color theorem in 1976, computer-generated proofs
have become a reality in mathematics and computer science. During the last
decade, we have seen formal proofs using verified proof assistants being used
to verify the validity of such proofs.
In this paper, we describe a formalized theory of size-optimal sorting
networks. From this formalization we extract a certified checker that
successfully verifies computer-generated proofs of optimality on up to 8
inputs. The checker relies on an untrusted oracle to shortcut the search for
witnesses on more than 1.6 million NP-complete subproblems.Comment: IMADA-preprint-c
Optimizing a Certified Proof Checker for a Large-Scale Computer-Generated Proof
In recent work, we formalized the theory of optimal-size sorting networks
with the goal of extracting a verified checker for the large-scale
computer-generated proof that 25 comparisons are optimal when sorting 9 inputs,
which required more than a decade of CPU time and produced 27 GB of proof
witnesses. The checker uses an untrusted oracle based on these witnesses and is
able to verify the smaller case of 8 inputs within a couple of days, but it did
not scale to the full proof for 9 inputs. In this paper, we describe several
non-trivial optimizations of the algorithm in the checker, obtained by
appropriately changing the formalization and capitalizing on the symbiosis with
an adequate implementation of the oracle. We provide experimental evidence of
orders of magnitude improvements to both runtime and memory footprint for 8
inputs, and actually manage to check the full proof for 9 inputs.Comment: IMADA-preprint-c
Endpoint in plasma etch process using new modified w-multivariate charts and windowed regression
Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS
International audienceWith the increased interest in energy efficiency, a lot of application domains experiment with Field Programmable Gate Arrays (FPGAs), which promise customized hardware accelerators with high-performance and low power consumption. These experiments possible due to the development of High-Level Languages (HLLs) for FPGAs, which permit non-experts in hardware design languages (HDLs) to program reconfigurable hardware for general purpose computing.However, some of the expert knowledge remains difficult to integrate in HLLs, eventually leading to performance loss for HLL-based applications. One example of such a missing feature is the efficient exploitation of the local memories on FPGAs. A solution to address this challenge is PolyMem, an easy-to-use polymorphic parallel memory that uses BRAMs. In this work, we present HLS-PolyMem, the first complete implementation and in-depth evaluation of PolyMem optimized for the Xilinx Design Suite. Our evaluation demonstrates that HLS-PolyMem is a viable alternative to HLS memory partitioning, the current approach for memory parallelism in Vivado HLS. Specifically, we show that PolyMem offers the same performance as HLS partitioning for simple access patterns, and outperforms partitioning as much as 13x when combining multiple access patterns for the same data structure. We further demonstrate the use of PolyMem for two different case studies, highlighting the superior capabilities of HLS-PolyMem in terms of performance, resource utilization, flexibility, and usability.Based on all the evidence provided in this work, we conclude that HLS-PolyMem enables the efficient use of BRAMs as parallel memories, without compromising the HLS level or the achievable performance
Characterization of multiple unique cDNAs encoding the major surface glycoprotein of rat-derivedPneumocystis carinii
Factors affecting pregnancy outcome of intrauterine insemination cycles in couples with favourable female characteristics
Predictive value of postwashed total progressively motile sperm count using CASA estimates in 6871 non-donor intrauterine insemination cycles
Effects of diesel exhaust particle exposure on a murine model of asthma due to soybean
Exposure to soybean allergens has been linked to asthma outbreaks. Exposure to diesel exhaust particles (DEP) has been associated with an increase in the risk of asthma and asthma exacerbation; however, in both cases the underlying mechanisms remain poorly understood, as does the possible interaction between the two entities.To investigate how the combination of soybean allergens and DEP can affect the induction or exacerbation of asthma in a murine model.BALB/c mice received intranasal instillations of saline, 3 or 5 mg protein/ml soybean hull extract (SHE), or a combination of one of these three solutions with DEP. Airway hyperresponsiveness (AHR), pulmonary inflammation in bronchoalveolar lavage, total serum immunoglobulin E and histological studies were assessed.A 5 mg protein/ml SHE solution was able by itself to enhance AHR (p = 0.0033), increase eosinophilic inflammation (p = 0.0003), increase levels of IL-4, IL-5, IL-13, IL-17A, IL-17F and CCL20, and reduce levels of IFN-γ. The combination of 5 mg protein/ml SHE with DEP also produced an increase in AHR and eosinophilic inflammation, but presented a slightly different cytokine profile with higher levels of Th17-related cytokines. However, while the 3 mg protein/ml SHE solution did not induce asthma, co-exposure with DEP resulted in a markedly enhanced AHR (p = 0.002) and eosinophilic inflammation (p = 0.004), with increased levels of IL-5, IL-17F and CCL20 and decreased levels of IFN-γ.The combination of soybean allergens and DEP is capable of triggering an asthmatic response through a Th17-related mechanism when the soybean allergen concentration is too low to promote a response by itself. DEP monitoring may be a useful addition to allergen monitoring in order to prevent new asthma outbreaks