Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches

This paper contributes to the maturity of the GALS NoC design practice by advocating for tight integration of GALS synchronization interfaces into NoC architecture building blocks. At the cost of re-engineering the input/output stages of NoC switches and network interfaces, this approach proves capable of materializing GALS NoCs with the same area and power of their synchronous counterparts, while reducing latency at the clock domain boundary. This design style is experimented in this paper with a mesochronous synchronizer and a dual-clock FIFO, which are tightly coupled with the switches of the xpipesLite NoC architecture

Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels

Adaptive body bias (ABB) and adaptive supply voltage (ASV) have been showed to be effective methods for post-silicon tuning of circuit properties to reduce variability. While their properties have been compared on generic combinational circuits or microprocessor circuit sub-blocks, the advent of multi-core systems is bringing a new application domain forefront. Global interconnects are evolving to complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterization of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the variability compensation efficiency of ABB vs ASV when put at work in two representative link architectures of today's ICs: a traditional full-swing interconnect and a low-swing signaling scheme for low-power communication. We provide guidelines for the post-silicon variability compensation of these communication channels

Cooperative Built-In Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels

This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC) for bisynchronous communication channels. Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way for the effective diagnosis and error detection. At-speed testing of stuck-at faults can be performed in less than 4000 cycles regardless of their size, with an hardware overhead of less than 30%

Tight Integration of GALS Interfaces into the NoC Architecture

This poster illustrates deep integration of of the synchronizer in the switch architecture of networks-on-chip, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. The poster compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip

We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within the SystemC simulation framework. The integration is based on the well-known concept of bus wrapper, that realizes the interface between the ISS and the simulator. The proposed solution uses an ISS-wrapper interface based on the standard gdb remote debugging interface, and implements two alternative schemes that differ in the amount of communication they require. The two approaches provide different degrees of tradeoff between simulation granularity and speed, and show significant speedup with respect to a micro-architectural, full SystemC simulation of the system description

Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style

A common technique to compensate process variation induced performance deviations during post-silicon testing consists of the dynamic adaptation of processor voltage. This however comes at a significant power cost. We envision multi supply voltage design (MSV) as a promising technique to mitigate such power overhead. Voltage islands are widely recognized as the state-of-the-art in MSV design. In this paper, we develop a novel design methodology that leverages voltage islands to compensate process variations through a commercial synthesis flow. Possible violation scenarios of performance requirements in fabricated chips are pre-characterized at design time through statistical static timing analysis. Then, during post-silicon testing the supply voltage of a proper number of voltage islands is raised depending on the actual violation scenario, thus bringing performance back within nominal values. Voltage islands are generated by exploiting cell proximity for minimal perturbation of performance pre-optimized placements

Abstract Modelling of Switching Elements for Optical Networks-on-Chip with Technology Platform Awareness

This paper reports the lessons learned in the abstraction process of the behaviour of switching elements for optical networks-on-chip, resulting in technology-annotated abstract models for the SystemC modelling and simulation environment. The paper points out the key physical effects that a designer should be aware of to properly assess effectiveness and feasibility of photonic switching fabrics. Moreover, the sources of inaccuracy are analysed when composing models of basic optical devices into higher order switching structures. Finally, a technique for modelling optical links into the SystemC framework is presented, by leveraging the pre-existing channel constructs. The findings of this paper capitalize on an extensive validation effort of abstract simulation models with FDTD simulations

Ultra-Low Latency NoC testing via Pseudo-Random Test Pattern Compaction

This paper aims at devising an optimized pseudorandom test methodology for NoCs and its architectural support. The guiding principle consists of using a test pattern compaction engine for generating minimal test lengths. We show the application of this principle driven by the objective to minimize test application time, at the cost of test wrapper complexity. The achieved design point results in a reduction of test application time by two orders of magnitude with respect to state-of-the-art test architectures for NoCs exploiting pseudo-random patterns

Networks-on-Chip: an Interconnection Fabric for Multiprocessor Systems-on-Chip

This chapter introduces the basic principles and guidelines for network-on-chip design. After providing a well-grounded motivation for this new communication paradigm, the chapter goes into the details of the NoC building blocks, presenting their design principles and the trade-offs spanned by implementation variants. Readers will be given the opportunity to become familiar withthe theoretical notions by analyzing a few case studies from real-life NoC prototypes. Finally, the key issue of topology design will be addressed from the perspective of both general-purpose as well as application-specific systems