An HPF Case Study of a Domain-Decomposition Based Irregular Application

. Data-parallel languages, in particular HPF, provide a highlevel view of operators overs parallel data structures and hide the details of data partitioning and communication. One of the most difficult issues in compiling such languages is managing irregular data-dependent parallelism. This paper presents the study of a realistic, but non adaptive irregular application. We show that HPF can easily express the natural parallelism of the application. Experimental results and a detailed examination of the compiler process are presented. 1 Introduction Data parallel languages, and especially High Performance Fortran (HPF) [1, 2] have been designed to make possible efficient and high-level parallel programming for distributed memory machines, in contrast to the lowlevel concurrent programming model based on explicit message-passing primitives. Even if many academic or proprietary data-parallel languages preceded it, HPF is very recent: the first language specification was completed in 93, ..

Conception avec règles en lambda d'une ROM 4-valuée

4-valued ROMS, with 2-bit per cell, are a valuable solution to increase memory density of Read Only Memories. Intel presentation of a 4-valued ROM didn't give details on the technological tolerances that are needed. We show that a 4-valued ROM can be designed with the French MultiProject Circuit (MPC) simplified design rules and large parameter tolerances. We compare it with the corresponding binary ROM using the same design rules.L'utilisation de ROMS 4-valuées, avec 2 bits par cellule, est une solution intéressante pour diminuer la taille des mémoires à lecture seule (ROM) de grosse capacité. Alors que la publication originale d'Intel ne donnait aucune information sur les tolérances technologiques, nous montrons la « faisabilité » d'une conception avec règles en λ sur le CMP français (Circuit Multi-Projets) d'une ROM 4-valuée que nous comparons avec la ROM binaire de même capacité utilisant les mêmes règles de dessin

Conception avec règles en lambda d'une ROM 4-valuée

L'utilisation de ROMS 4-valuées, avec 2 bits par cellule, est une solution intéressante pour diminuer la taille des mémoires à lecture seule (ROM) de grosse capacité. Alors que la publication originale d'Intel ne donnait aucune information sur les tolérances technologiques, nous montrons la « faisabilité » d'une conception avec règles en λ sur le CMP français (Circuit Multi-Projets) d'une ROM 4-valuée que nous comparons avec la ROM binaire de même capacité utilisant les mêmes règles de dessin

3D morphological analysis of copper foams as current collectors for Li-ion batteries by means of X-ray tomography

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High Level Tranforms to reduce energy consumption of signal and image processing operators

International audienceHigh Level Synthesis for Systems on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perform some high level transforms.This paper evaluates the impact of such high level transforms for ASICs. We have evaluated recursive and non recursive filters for signal processing an morphological filters for image processing. We show that the impact of HLTs to reduce energy consumption is high : from ×3.4 for one 1D filter up to ×5.6 for cascaded 1D filters and about ×3.5 for morphological 2D filters

Interfacial stability and electrochemical behavior of Li/LiFePO 4 batteries using novel soft and weakly adhesive photo-ionogel electrolytes

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