Design and Selection of Buffers for Minimum Power-Delay Product

Using explicit modeling of delays we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to standard cell library in comparing implementations for different selection alternatives. 1. Introduction Driving buffers have been extensively used to control delays on combinatorial paths. Values of tapering factors were determined depending on the performance modeling level and on the physical representation of the cells involved with a common objective: minimizing the delay of paths. In an initial simple theory Lin and Linholm [1] introduced the fixed tapered buffer where the minimum propagation delay time is achieved when the..

RAPIDO Testing of Assisted Write and Read operations for SRAMs

Lowering the supply voltage of Static Random-Access Memories (SRAM) is key to reduce power consumption, however since this badly affects the circuit performances, it might lead to various forms of loss of functionality. In this work, we present silicon results showing significant yield improvement, achieved with write and read assist techniques on a 6T high- density bitcell manufactured in 40 nm technology. Data is successfully modeled with an original spice-based method that allows reproducing at high computing efficiency the effects of static negative bitline write assist, the effects of static wordline underdrive read assist, while the effects of read ability losses due to low-voltage operations on the yield are not taken into account in the model

UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM

session: SOI Circuit DesignInternational audienceThis work investigates the impact of Random Telegraph Signal (RTS) noise on a 6-Transistor Single-P-Well Static Random Access Memory (6T-SRAM) in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. RTS noise impact is observed through Write-Ability measurements on a 143Kb SRAM macro. A SPICE-level bias- and time-dependent RTS model peculiar to UTBB FD-SOI, introducing the back-gate as a second RTS noise source and considering the front- and back-gate coupling, is used for simulations to confirm silicon observations. It is shown that the body-biasing feature of UTBB FD-SOI does not introduce critical RTS noise compared to the one originated from the device front gate

RAPIDO Testing of Assisted Write and Read operations for SRAMs

Lowering the supply voltage of Static Random-Access Memories (SRAM) is key to reduce power consumption, however since this badly affects the circuit performances, it might lead to various forms of loss of functionality. In this work, we present silicon results showing significant yield improvement, achieved with write and read assist techniques on a 6T high- density bitcell manufactured in 40 nm technology. Data is successfully modeled with an original spice-based method that allows reproducing at high computing efficiency the effects of static negative bitline write assist, the effects of static wordline underdrive read assist, while the effects of read ability losses due to low-voltage operations on the yield are not taken into account in the model

Illness representation and treatment beliefs in liver transplantation: An exploratory qualitative study

International audienc

RAPIDO Testing of Assisted Write and Read operations for Ultra-Low Power SRAMs

W07.12.4International audienc

Performances and mechanistic investigations of a triphosphine trioxide/ionic liquid system for rare earth extraction

International audienc