Agraphs: Definition, implementation and tools

Agraphs are a graph-based language representation, transformation and exchange format. In the same vein as XML, Agraphs form a general data representation mechanism that needs to be instantiated in different specific applications. In this paper, we present the Agraphs data structure, programming interface and related tools, identify their main features with respect to exchange format characteristics, and compare them to other existing exchange formats. These different features are illustrated on an instance of Agraphs for modular Petri nets

haRVey: combining reasoners

We present the architecture of the oncoming version of the SMT (Satisfiability Modulo Theories) solver haRVey. haRVey checks the satisfiability of a formula written in a first-order language with interpreted symbols from various theories. Its new architecture is original, first in the sense that it is a combination of reasoners, rather than the traditional combination of decision procedures. Second, one of these reasoners is a full-featured first-order saturation-based prover. Finally, some of those reasoners in the combination may only be sporadically activated not using computer time when inactive. We believe those new features will contribute to the efficiency and expressivity of the new version of the tool

Semantics of a Verification-Oriented Subset of VHDL

. This paper gives operational semantics for a subset of VHDL in terms of abstract machines. Restrictions to the VHDL source code are the finiteness of data types, and the absence of quantitative timing informations. The abstract machine of a design unit is built by composition of the abstract machines for its embedded processes and blocks. The kernel process in our model is distributed among the composed machines. One transition of the final abstract machine models a VHDL delta cycle. This model can be used for symbolic model checking and equivalence verification. 1 Introduction Giving a formal definition of the semantics of VHDL [7] is of highest importance for synthesis and formal verification. Many different approaches have been proposed to fulfill this need, see eg [1, 3, 4, 5, 8, 9, 10, 11]. A first conclusion can be drawn from a study of these works: one has to trade off the number of VHDL features modeled, and the practical usefulness of the semantics. VHDL is a very complex l..

Light-Weight Theorem Proving for Debugging and Verifying Units of Code

Software bugs are very difficult to detect even in small units of code. Several techniques to debug or prove correct such units are based on the generation of a set of formulae whose unsatisfiability reveals the presence of an error. These techniques assume the availability of a theorem prover capable of automatically discharging the resulting proof obligations. Building such a tool is a difficult, long, and error-prone activity. In this paper, we describe techniques to build provers which are highly automatic and flexible by combining state-of-the-art superposition theorem provers and BDDs. We report experimental results on formulae extracted from the debugging of C functions manipulating pointers showing that an implementation of our techniques can discharge proof obligations which cannot be handled by Simplify (the theorem prover used in the ESC/Java tool) and performs much better on others. 1