Investigations of electron-beam and optical induced damage in high mobility SiGe heterostructures

Modulation-doped two dimensional electron gases (2DEGs) grown on Si0.7Ge0.3 virtual substrates were investigated. Low temperature measurements were used to characterise the uniformity of the wafers and annealing studies demonstrated that high annealing temperatures (above 600°C) destroyed the electrical properties. Studies of excimer irradiation of the 2DEG material demonstrated that only surface damage was induced, but the subsequent annealing of this damage reduced the carrier density in the material, suggesting strain relaxation of the strained Si cap. Electron beam irradiation experiments at 40 keV and PMMA doses showed charging effects at room temperature but little damage. Finally a number of narrow channel devices were fabricated using 300 keV electrons and characterised at low temperature to estimate the range of the electron-beam induced damage

Investigation of the zero-field 2D "metallic" state with r(s) and k(F)l controlled independently

We compare the rise in resistivity with increasing temperature in the “metallic” regime for a range of electron densities and for several values of substrate bias. This allows the strength of Coulomb interactions (rS) and of disorder (1/kFl) to be controlled independently. For temperatures well below the Fermi temperature, our data obey a scaling law where kFl, and not rS, is the crucial parameter, suggesting that the “metallic” state is not a novel state caused by interactions

Si/Si1-xGex heterostructure field effect transistors fabricated using a low thermal budget CMOS process

Strained Si/Si0.75Ge0.25 heterostructure field effect transistors (HFETs) have been fabricated using a modified, low-thermal budget CMOS process with deposited gate oxides. Transmission electron microscopy demonstrates the integrity of the strained-Si quantum well after processing. The transconductances of the HFET devices are higher than the similarly processed Si MOSFET devices. Electrical characterisation data is presented which suggest that thinner gate oxides, higher Ge contents in the virtual substrate and optimisation of the p-type substrate doping profile will improve device performance

n-type Si/SiGe resonant tunnelling diodes

Resonant tunnelling diodes (RTDs) have been fabricated using Si/SiGe heterolayers which demonstrate room temperature performance comparable to III–V technology. Peak current densities up to 282 kA cm−2 with peak-to-valley current ratios (PVCRs) of 2.4 have been demonstrated at room temperature in devices with dimensions of 5×5 μm2. Scaling the device size demonstrates that the peak current density is inversely proportional to the device area. It is suggested that this is related to thermal limitations in the device structure. Estimates are also produced for the maximum frequency of oscillations of the diodes which suggest that oscillators may operate with speeds comparable to III–V diodes

Silicon quantum integrated circuits

No abstract available

Silicon quantum integrated circuits

No abstract available

Silicon quantum integrated circuits - an attempt to fabricate silicon-based quantum devices using CMOS fabrication techniques

An introduction to the methodology, design concepts, fabrication routes and potential applications is presented of research to fabricate quantum devices on a complementary metal oxide semiconductor (CMOS) fabrication line. Si/Si1-xGex heterostructure field effect transistors, velocity modulation transistors and resonant tunnelling diodes are considered and initial fabrication stages discussed