MODALITY OF TREATMENT IN ESSENTIAL THROMBOCYTHEMIA

Essential thrombocytosis (ET) is clonal chronic myeloproliferative disorder which originates from abnormality of a multipotent hematopoietic stem cell.It is characterized by an increased platelet count, megakaryocytic hyperplasia and by hemorrhagic or thrombotic tendency. Symptoms and signs may include weakness, headaches, paresthesias, bleeding, splenomegaly, and digital ischemia. ET patients showed equal or slightly shorter survival than age- and sex-matched healthy population. Major causes of death were thrombotic and hemorrhagic complications or malignant progression due to both the natural history of the disease and, possibly, the use of chemotherapeutic agents.Diagnostic criteria for essential thrombocythemia were proposed in 2005 by the PVSG and demand diagnosis of exclusion.Myelosuppressive therapy to lower the platelet count usually consists of hydroxyurea, interferon alpha or anagrelide. Hydroxyurea is the most commonly used treatment, because of its efficacy, low cost and rare acute toxicity. Interferon alpha is a biological response modifier. It is not known to be teratogenic and does not cross the placenta, and is often the treatment of choice during pregnancy. Anagrelid suppresses bone marrow megakaryocytes by interfering with the maturation process and decreasing platelet production without affecting other blood cell lines. Low-dose aspirin may be used to control microvascular symptoms.Recommendations for management of patients with essential thrombocythemia were given by ASH. From a treatment standpoint, hydroxyurea is now confirmed to be the drug of choice for high-risk patients with essential thrombocythemia. Interferon alpha and anagrelide are reasonable second-line agents. Low-risk patients should receive low-dose aspirin alone. For the intermediate-risk patients, a consensus could not be reached on a recommendation for platelet-lowering treatment

Design of Digital SoC for Operation at High Temperatures

There is a growing demand for Systems-on-Chip, integrating microprocessors, on-chip memories, data converters and a variety of sensors, which are capable of reliable operation at high temperatures. For instance, modern aircraft industry demands microcontrollers and electric motors to operate at high temperatures, in order to replace present hydraulic structures. This thesis explains how to design digital SoC which are capable of reliable operation at high temperatures. The essential part of this thesis focuses on the design, implementation, fabrication and high-temperature measurements of on-chip Latch based SRAM, PowerPC e200 based microcontroller, digital temperature sensor and Flash A/D converter. Embedded on-chip SRAM modules are one of the most important components in the modern SoC. We analyze thermally-caused failures in the 6T SRAM cell and elaborate on its reliability. Further, we show that Latch based SRAM modules are preferable to 6T SRAM for reliable operation beyond 150C, by comparing two 1kB SRAM modules implemented in standard 0.18um SOI CMOS process. We demonstrate reliable SRAM operation at 275C (fmax = 10MHz, Ptot = 400mW), that is by far the highest reported operating temperature for digital on-chip SRAM module. Designing SoCs for reliable operation at elevated temperatures is a significant challenge, due to increased static leakage current, reduced carrier mobility, and increased electromigration. We propose to customize a PowerPC e200 based SoC by using a dynamically reconfigurable clock frequency, exhaustive clock gating, and electromigration-resistant power distribution network. We fabricated a 20x9mm2 chip implementing this design in 0.35um Bulk CMOS process. We present worldâs first PowerPC based SoC for reliable operation at 225C (fmax = 30MHz, Ptot = 1.2W). This design outperforms previously reported PowerPC based SoCs, which are not operational at temperatures beyond 125C. The on-chip measurements of the p-n junction temperature allow reliability improvements for the SoC that operates at high temperatures. Low-resolution temperature measurements are efficiently used for adjusting the optimal operation frequency and supply voltage. We used the Time-to-Digital conversion technique to design a fully-digital temperature sensor. We designed and simulated a fully-digital 5bit temperature sensor for 10C resolution temperature measurements in between Tj,min = -45C and Tj,max = 125C. Further, using a single clock cycle Time-to-Digital conversion technique, we present a fully-digital 5bit Pulse based Flash ADC implemented in 0.18um Bulk CMOS process. Measurement results demonstrate the state-of-the-art power efficiency result of 450 fJ/conv (fmax = 83MHz, Ptot = 900uW)

A Sub-mW Pulse-Based 5-bit Flash ADC with a Time-Domain Fully-Digital Reference Ladder

Journal article A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder: A Katic, Nikola; Cojbasic, Radisav; Schmid, Alexandre; Leblebici, Yusuf Published in: Microelectronics Journal (ISSN: 0026-2692), vol. 46, num. 12, p. 1343-1350 Oxford: Elsevier Sci Ltd, 2015 The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion (TDC) technique is introduced which performs the complete conversion within a single clock cycle. The measurement results show that the proposed 5-bit converter achieves an 80 MHz sampling rate while consuming 900 mu W of power from the 1.8 V supply voltage. The prototype ADC is developed in a 180 nm standard CMOS technology and achieves the power efficiency of 445 fJ/conversion which is comparable to many existing state-of-the-art flash ADCs. The measured performance is achieved without any design optimization or circuit calibration techniques confirming the promising benefits of the proposed topology. Thanks to the fully-digital structure, the circuit enables a robust and compact implementation which is very convenient for interleaving and beneficial for many potential applications

Machine Learning Classification of Cervical Tissue Liquid Based Cytology Smear Images by Optomagnetic Imaging Spectroscopy

Semi-automated system for classification of cervical smear images based on Optomagnetic Imaging Spectroscopy (OMIS) and machine learning is proposed. Optomagnetic Imaging Spectroscopy has been applied to screen 700 cervical samples prepared according to Liquid Based Cytology (LBC) principles and to record spectra of the samples. Peak intensities and peak shift frequencies from the spectra have been used as features in classification models. Several machine learning algorithms have been tested and results of classification have been compared. Results suggest that the presented approach can be used to improve standard LBC screening tests for cervical cancer detection. Developed system enables detection of pre-cancerous and cancerous states with sensitivity of 79% and specificity of 83% along with AUC (ROC) of 88% and could be used as an improved alternative procedure for cervical cancer screening. Moreover, this can be achieved via portable apparatus and with immediately available results

Packaging technologies for high temperature control electronics

Current low temperature electronics (175°C) for prolonged periods of time require packaging technologies that have to tackle many new problems. At high temperatures traditionally used materials such as organic circuit boards, adhesives and standard solders degrade rapidly or undergo changes in structure and properties. An even more critical issue than high-temperature survivability is resistance to temperature cycling. Thermal mismatch between organic boards and semiconductor dies leads to high thermomechanical strains during swings from high to low temperature extremes, which can make an otherwise high temperature resistant assembly fail after a relatively low number of cycles. This work focuses on the packaging technologies for high temperature control modules, those with logical and signal conditioning applications. Although control modules share many similarities with power modules, they present their own unique design challenges, such as significantly higher complexity and a limitation of compatible materials. Here, recent research on substrates, die attach technologies and wirebond interconnects suited for high temperature ICs are presented along with packaging technologies for discrete components (capacitors and resistors) with the aim of identifying the current best solutions. Test vehicles for the various technologies were constructed and were subjected to high temperature storage at temperatures higher than 200°C. They were analysed in terms of degradation (i.e. loss in shear strength, pull strength, change in resistance, etc.). In parallel, a separate set of samples were subjected to temperature cycles from -20°C to 180°C and then analysed using the same tests as before for comparison. The combined data allow a recommendation to be made on how to assemble a viable control module such as one based on an SOI microcontroller designed at EPFL to operate at high temperatures. Keywords: High temperature packaging, CPUs and MCUs, Reliabilit

Tripled Coincidence Points of Mappings in Partially Ordered 0-Complete Partial Metric Spaces

In this paper, we introduce the concept of a tripled coincidence point for a pair of nonlinear contractive mappings F : X3 → X and g : X → X in partially ordered 0-complete partial metric spaces and obtain existence and uniqueness theorems. Our results generalize, extend, unify and complement recent tripled coincidence point theorems established by Marin Borcut, Vasile Berinde [M. Borcut, V. Berinde, Tripled coincidence theorems for contractive type mappings in partially ordered metric spaces, Applied Mathematical and Computation 218 (2012) 5929-5935], Marin Borcut [M. Borcut, Tripled coincidence theorems for contractive type mappings in partially ordered metric spaces, Applied Mathematical and Computation 218 (2012) 7339-7346], Hassen Aydi, Erdal Karapinar, Mihail Postolache [H. Aydi, E. Karapinar, M. Postolache, Tripled coincidence point theorems for weak ϕ−contractions in partially ordered metric spaces, Fixed Point Theory and Applications 2012, 2012:44, doi: 10.1186/1687-1812-2012-44] and Binayak S. Choudhury, Erdal Karapinar and Amaresh Kundu [B. Choudhury, E. Karapinar, A. Kundu, Tripled coincidence point theorems for nonlinear contractions in partially ordered metric spaces, International Journal of Mathematics and Mathematical Sciences,2012, in press]. Examples to support our new results are given.<br /