Linkage analysis for drought tolerance in kharif rice of Assam using microsatellite markers

371-375Drought stress in rainfed ecosystem significantly limits the production of Ranjit, the most predominant high yielding rice variety of Assam. A mapping population comprising 85 F4 individuals between Ranjit and a drought tolerant cultivar, ARC10372 was developed and genotyped with 80 microsatellite markers in order to understand the genetic basis of drought tolerance. The linkage map constructed based on a framework linkage map using these markers showed that the marker loci were distributed across 12 chromosomes spanning a distance of 273.4 cM with an average interval of 3.41 cM between marker loci. Most of the marker loci were found to be in good fit with the expected Mendelian segregation ratio; however, thirteen marker loci in total showed segregation distortion on six chromosomes. The linkage map generated in the study will facilitate mapping of quantitative trait loci imparting drought tolerance in rice of Assam and their map-based cloning

SSR marker-based DNA fingerprinting of Sub1 introgressed lines in the background of traditional rice varieties of Assam India

350-356Rice varieties are usually characterized by agro-morphological descriptors used for seed certification and seed characterization by following distinctiveness, uniformity, and stability (DUS) test. But in fact, these primary distinguishing morphological descriptors among rice varieties are very limited and hence face problems to distinguish germplasm accessions. Germplasm certification in NBPGR requires a DNA fingerprinting profile to explain germplasm uniqueness compared to existing varieties. Varietal identification has gained a key role worldwide, particularly in plant variety protection. Sixty-two morphological descriptors studies have shown the Sub1 introgressed advanced lines E-6, C-210, C-196, 1189-1 and 1160-1 are distinct from the other varieties for more than 15morphological traits, based on these variations the lines were selected for DNA fingerprinting. About68 SSRs markers were used for DNA fingerprinting in seven genotypes, two of which were parents (Ranjit, Bahadur) and three Sub1 introgressed advanced lines (E6, C210, C196) in Ranjit background, and two Sub1 introgressed advanced lines (1189-1, 1160-1) in Bahadur background. DNA fingerprinting was done on these genotypes of rice using SSR markers. Among the 68 SSR markers, total 65 markers were amplified and three were found not amplified. Out of 65 markersfour of them viz. RM 152, RM 172, RM 251, and RM 346 showed better polymorphism with amplicon size ranges from 155-163 bp, 150-159 bp, 137-147 bp, and 166-175 bp, respectively, and remaining 61 showed monomorphic amplification. Therefore, SSR (Simple-sequence repeats) based DNA fingerprinting helped to differentiate Ranjit, Bahadur, E-6, C-210, C-196, 1189-1, and 1160-1. Hence, the research reveals that newly developed high-yielding Sub1 introgressed advanced lines in the background of traditional Assam rice varieties (Ranjit and Bahadur) are unique in their identity

Generic Routing Rules and a Scalable Access Enhancement for the Network-on-Chip RECONNECT

RECONNECT is a Network-on-Chip using a honeycomb topology. In this paper we focus on properties of general rules applicable to a variety of routing algorithms for the NoC which take into account the missing links of the honeycomb topology when compared to a mesh. We also extend the original proposal [5] and show a method to insert and extract data to and from the network. Access Routers at the boundary of the execution fabric establish connections to multiple periphery modules and create a torus to decrease the node distances. Our approach is scalable and ensures homogeneity among the compute elements in the NoC. We synthesized and evaluated the proposed enhancement in terms of power dissipation and area. Our results indicate that the impact of necessary alterations to the fabric is negligible and effects the data transfer between the fabric and the periphery only marginally

SSR marker-based DNA fingerprinting of Sub1 introgressed lines in the background of traditional rice varieties of Assam India

Rice varieties are usually characterized by agro-morphological descriptors used for seed certification and seed characterization by following distinctiveness, uniformity, and stability (DUS) test. But in fact, these primary distinguishing morphological descriptors among rice varieties are very limited and hence face problems to distinguish germplasm accessions. Germplasm certification in NBPGR requires a DNA fingerprinting profile to explain germplasm uniqueness compared to existing varieties. Varietal identification has gained a key role worldwide, particularly in plant variety protection. Sixty-two morphological descriptors studies have shown the Sub1 introgressed advanced lines E-6, C-210, C-196, 1189-1 and 1160-1 are distinct from the other varieties for more than 15morphological traits, based on these variations the lines were selected for DNA fingerprinting. About68 SSRs markers were used for DNA fingerprinting in seven genotypes, two of which were parents (Ranjit, Bahadur) and three Sub1 introgressed advanced lines (E6, C210, C196) in Ranjit background, and two Sub1 introgressed advanced lines (1189-1, 1160-1) in Bahadur background. DNA fingerprinting was done on these genotypes of rice using SSR markers. Among the 68 SSR markers, total 65 markers were amplified and three were found not amplified. Out of 65 markersfour of them viz. RM 152, RM 172, RM 251, and RM 346 showed better polymorphism with amplicon size ranges from 155-163 bp, 150-159 bp, 137-147 bp, and 166-175 bp, respectively, and remaining 61 showed monomorphic amplification. Therefore, SSR (Simple-sequence repeats) based DNA fingerprinting helped to differentiate Ranjit, Bahadur, E-6, C-210, C-196, 1189-1, and 1160-1. Hence, the research reveals that newly developed high-yielding Sub1 introgressed advanced lines in the background of traditional Assam rice varieties (Ranjit and Bahadur) are unique in their identity

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE