A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems

An Analog to Digital Converter (ADC) using the low duty-cycle nature of pulse-based Ultra Wide-Band (UWB) communications to reduce its power consumption is proposed. Implemented in CMOS 180 nm technology, it can capture a 5 ns window at 4 GS/s each 100 ns, which corresponds to the acquisition of one UWB pulse at the pulse repetition rate of 10 mega pulses per second (Mpps). By using time-interleaved Redundant Signed Digit (RSD) ADCs, the complete ADC occupies only 0.15 mm2 and consumes only 1.4 mW from a 1.8 V power supply. The ADC can be operated in two modes using the same core circuits (operational transconductance amplifier, comparators, etc.). The first mode is the standard RSD doubling mode, while the second mode allows improving the signal-to-noise ratio by adding coherently the transmitted pulses of one symbol. For example, for audio applications, a 300 kbps data rate and processing gain up to 15 dB can be achieved at a clock frequency of 10 MHz

Optically Pumped Space Cs Clock TRL5

International audienc

Optically Pumped Space Cs Clock TRL5

International audienc

A 0.8V 2.4GHz 1Mb/s GFSK RF transceiver with on-chip DC-DC converter in a standard 0.18µm CMOS technology

A low-energy 2.4GHz RF transceiver supporting 1Mb/s Gaussian Frequency-Shift Keying modulation and designed to run on a 1.5V battery is implemented in a standard 0.18μm CMOS technology. The integrated DC-DC converter can provide up to 100mA to an external load besides the current required by the transceiver. The transmitter current at 0dBm nominal output power is 11.9mA. The receiver draws 11.4mA and presents a sensitivity of -82.5dBm at a bit-error rate of 0.1% with the on-chip DC-DC converter delivering a total of 120mA. The transceiver is able to operate at a supply voltage as low as 0.8V

Optically pumped Cs space clock development

International audienc