Performance of novel VUV-sensitive Silicon Photo-Multipliers for nEXO

Liquid xenon time projection chambers are promising detectors to search for neutrinoless double beta decay (0$\nu \beta \beta$), due to their response uniformity, monolithic sensitive volume, scalability to large target masses, and suitability for extremely low background operations. The nEXO collaboration has designed a tonne-scale time projection chamber that aims to search for 0$\nu \beta \beta$ of \ce{^{136}Xe} with projected half-life sensitivity of $1.35\times 10^{28}$~yr. To reach this sensitivity, the design goal for nEXO is $\leq$1\% energy resolution at the decay $Q$-value ($2458.07\pm 0.31$~keV). Reaching this resolution requires the efficient collection of both the ionization and scintillation produced in the detector. The nEXO design employs Silicon Photo-Multipliers (SiPMs) to detect the vacuum ultra-violet, 175 nm scintillation light of liquid xenon. This paper reports on the characterization of the newest vacuum ultra-violet sensitive Fondazione Bruno Kessler VUVHD3 SiPMs specifically designed for nEXO, as well as new measurements on new test samples of previously characterised Hamamatsu VUV4 Multi Pixel Photon Counters (MPPCs). Various SiPM and MPPC parameters, such as dark noise, gain, direct crosstalk, correlated avalanches and photon detection efficiency were measured as a function of the applied over voltage and wavelength at liquid xenon temperature (163~K). The results from this study are used to provide updated estimates of the achievable energy resolution at the decay $Q$-value for the nEXO design

Track E Implementation Science, Health Systems and Economics

Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/138412/1/jia218443.pd

Track D Social Science, Human Rights and Political Science

Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/138414/1/jia218442.pd

The impact of etched trenches geometry and dielectric material on the electrical behaviour of SOI self-switching diodes

Hole electrical transport in a p-doped nanochannel defined between two L-shape etched trenches made on a silicon-on-insulator substrate is investigated using a TCAD-Medici simulator. We study the impact of the etched trenches' geometry and dielectric filling materials on the current–voltage characteristics of the device. Carrier accumulation on frontiers defined by the trenches causes a modulation of the hole density inside the conduction channel as the bias voltage varies and this gives rise to a diode-like characteristic. For a 1.2 µm-long channel, plots of the electric field distribution show that a nonlinear transport regime is reached at a moderate reverse and forward bias of ± 2 V. Plots of the carrier velocity along the conduction channel show that holes remain hot for a few hundreds of nm outside the nanometre-wide channel, at a bias of ± 10 V. Filling the etched trenches with a high-κ dielectric material gives rise to a lower threshold voltage, Vth. A similar decrease of Vth is also achieved by reducing the longitudinal and/or the transverse trench width. Our simulation results provide useful design guidelines for future integrated self-switching-diode-based circuits

First Report on Self-Switching-Diodes in SOI

The work on SOI shows that SSDs can be compatible with advanced CMOS on SOI technologies, which greatly enhances the possibilities to practically use SSDs. One of the most significant advantages of SSDs is the remarkably simple process requiring only to create trenches in a semiconductor film. By combining a few SSDs, simple logic gates can be fabricated also in one lithography step (Song, 2003). The SSDs can also be used as memory cells working at room temperature as demonstrated in ref. 6. Furthermore, one can form a lateral gate on one side of the channel thus making a self-switching transistor (SST) opening more possibilities for applications. These various devices are under fabrication on SOI and characterisation in our group. We believe that that SSDs on SOI may provide remarkable simplicity and flexibility in circuit design and fabricatio