On Spike-Timing-Dependent-Plasticity, Memristive Devices, and Building a Self-Learning Visual Cortex

In this paper we present a very exciting overlap between emergent nanotechnology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nanotechnology devices to the biological synaptic update rule known as spike-time-dependent-plasticity (STDP) found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage or flux driven memristors and focus our discussions on a behavioral macro-model for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forward but also backward. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We will briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We will illustrate how a V1 visual cortex layer can assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim of this paper is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three-terminal memristive type devices. All files used for the simulations are made available through the journal web site1

Atracción de escolítidos a trampas cebadas con etanol y monoterpenos en montes de Pinus pinea

Se presentan resultados de ensayos de campo para la atracción de escolítidos mediante el empleo de trampas cebadas (tipo Crossvane) con compuestos de presumible actividad cairomonal. Se realizaron tres experimentos (diciembre-2010 a enero-2011, abril a mayo de 2011 y octubre a noviembre de 2011) en cuatro parcelas con actividad relevante de Tomicus destruens y similar estado selvícola (términos municipales de Cartaya y Aljaraque. Huelva). Los objetivos parciales fueron: comparar la evolución temporal de capturas, probar la eficacia de distintas dosis de etanol y su actividad sinérgica con a-pineno, y explorar la actividad de monoterpenos en solitario o combinados (a-pineno, limoneno y terpinoleno). Seis especies de Scolytinae fueron capturadas de forma mayoritaria: T. destruens, Orthotomicus erosus, Hylastes linearis, Crypturgus mediterraneus, Carphoborus pini e Hylurgus ligniperda. Las combinaciones que emitieron la mezcla de etanol y a-pineno en diversas dosis capturaron más T. destruens y O. erosus que las que emitieron etanol solamente, aunque las diferencias no fueron significativas. En primavera abundaron H. linearis y C. mediterraneus. La presencia de limoneno pareció reducir las capturas de T. destruens. El impacto de captura de varias especies depredadoras (Thanasimus formicarius, Rhizophagus spp. y Aulonium ruficorne) que se redujo notablemente en trampas provistas de rejilla y ranuras de escape

Sistema de reconocimiento de caracteres de alta velocidad basado en eventos

Comunicación presentada al "XXVI Simposio de la URSI" celebrado en Leganés (España) del 7 al 9 de Septiembre del 2011.Spike-based processing technology is capable of very high speed throughput, as it does not rely on sensing and processing sequences of frames. Besides, it allows building complex and hierarchically structured cortical-like layers for sophisticated processing. In this paper we summarize the fundamental properties of this sensing and processing technology applied to artificial vision systems and the AER (Address Event Representation) protocol used in hardware spiking systems. Finally a four-layer system is described for character recognition. The system is slightly based on the Fukushima's Neocognitron. Realistic simulations using figures of already existing AER devices are provided, which show recognition delays under 10μs.Este trabajo ha sido financiado en parte por el proyecto TEC2009-10639-C04-01 (VULCANO) y el proyecto andaluz P06-TIC-01417 (Brain System). JAPC ha sido financiado por el proyecto andaluz P06-TIC-01417 (Brain System).Peer Reviewe

Red neuronal convolucional rápida sin fotogramas para reconocimientos de dígitos

Comunicación presentada al "XXVI Simposio de la URSI" celebrado en Leganés (España) del 7 al 9 de Septiembre del 2011.In this paper a bio-inspired six-layer convolutional network (ConvNet) non-frame based for digit recognition is shown. The system has been trained with the backpropagation algorithm using 32x32 images from the MNIST database. The system can be implemented with already physically available spike-based electronic devices. 10000 images have been coded into events separated 50ns to test the non-frame based ConvNet system. The simulation results have been obtained using actual performance figures for existing AER (Address Event Representation) hardware components. We provide simulation results of the system showing recognition delays of a few microseconds from stimulus onset with a recognition rate of 93%. The complete system consists of 30 convolution modules.Este trabajo ha sido financiado en parte por el proyecto TEC2009-10639-C04-01 (VULCANO) y el proyecto andaluz P06-TIC-01417 (Brain System). JAPC ha sido financiado por el proyecto andaluz P06-TIC-01417 (Brain System).Peer Reviewe

Fast vision through frameless event-based sensing and convolutional processing: Application to texture recognition

Address-event representation (AER) is an emergent hardware technology which shows a high potential for providing in the near future a solid technological substrate for emulating brain-like processing structures. When used for vision, AER sensors and processors are not restricted to capturing and processing still image frames, as in commercial frame-based video technology, but sense and process visual information in a pixel-level event-based frameless manner. As a result, vision processing is practically simultaneous to vision sensing, since there is no need to wait for sensing full frames. Also, only meaningful information is sensed, communicated, and processed. Of special interest for brain-like vision processing are some already reported AER convolutional chips, which have revealed a very high computational throughput as well as the possibility of assembling large convolutional neural networks in a modular fashion. It is expected that in a near future we may witness the appearance of large scale convolutional neural networks with hundreds or thousands of individual modules. In the meantime, some research is needed to investigate how to assemble and configure such large scale convolutional networks for specific applications. In this paper, we analyze AER spiking convolutional neural networks for texture recognition hardware applications. Based on the performance figures of already available individual AER convolution chips, we emulate large scale networks using a custom made event-based behavioral simulator. We have developed a new event-based processing architecture that emulates with AER hardware Manjunath's frame-based feature recognition software algorithm, and have analyzed its performance using our behavioral simulator. Recognition rate performance is not degraded. However, regarding speed, we show that recognition can be achieved before an equivalent frame is fully sensed and transmitted.This work was supported in part by the Spanish Ministry of Education and Science under Grant TEC-2006-11730-C03-01 (SAMANTA2), be the Andalusian regional government under Grant P06-TIC-01417 (Brain System), and by the European Union (EU) Grants IST-2001-34124 (CAVIAR) and 216777 (NABAB). The work of J. A. Pérez-Carrasco was supported by a doctoral scholarship as part of research project Brain System.Peer reviewe

Estudio comparativo de la ecología de la procesionaria del pino ("Thaumetopoea pityocampa schiff.") en el Parque Natural de Doñana y P.N. Cazorla Segura y las Villas

Estimar la diapausa de una zona siempre ha sido uno de los principales problemas en la lucha contra la procesionaria del pino. Los análisis de enterramientos son muy laboriosos y en la mayoría de los casos no ofrecen datos significativos, una forma de estimar este dato podría consistir en estudiar la homogeneidad de una muestra de puestas. En el caso de este trabajo se analiza este parámetro en dos áreas de experimentación, una situada en el Parque Natural de Cazorla Segura y Las Villas (donde existe diapausa), y otra en el Parque Natural del Entorno de Doñana (donde no existe diapausa).Estimate diapause in an area, has always been one of the main problems in fight against the pine processionary moth. Subterraneans analysis require lots of work and in the most cases the results obteined aren't significant. Studying the homogeneity of the egg-batches sample could be a method to estimate this parameter. In this work we use it withim two research areas placed, one in the Natural Park of "Cazorla, Segura y las Villas" (were diapause exist), and the other in the Natural Park of "Doñana" (were there isn't diapause)

On real-time AER 2-D convolutions hardware for neuromorphic spike-based cortical processing

In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address-event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16 ×16 has been implemented with programmable kernel size of up to 16 × 16. The chip has been fabricated in a standard 0.35-μm complimentary metal-oxide-semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog-digital circuit techniques. Because of the low currents involved (down to nanoamperes or even picoamperes), an important amount of pixel area is devoted to mismatch calibration. The rest of the chip uses digital circuit techniques, both synchronous and asynchronous. The fabricated chip has been thoroughly tested, both at the pixel level and at the system level. Specific computer interfaces have been developed for generating AER streams from conventional computers and feeding them as inputs to the convolution chip, and for grabbing AER streams coming out of the convolution chip and storing and analyzing them on computers. Extensive experimental results are provided. At the end of this paper, we provide discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems. © 2008 IEEE.This work was supported by the European Commission under Grants IST-2001-34124 (CAVIAR) and 216777 (NABAB), the Spanish Ministry of Education and Science under Grants TIC-2000-0406-P4 (VICTOR), TIC-2003-08164-C03-01 (SAMANTA), and TEC2006-11730-C03-01 (SAMANTA2), and the Junta de Andalucia under Grant TIC-1417 (Brain System). The work of R. Serrano-Gotarredona was supported by the Spanish Ministry of Education and Science under the FPU scholarships. The work of J. A. Pérez-Carrasco was supported by a scholarship from Junta de Andalucia.Peer Reviewe

Advanced vision processing systems: Spike-based simulation and processing

In this paper we briefly summarize the fundamental properties of spike events processing applied to artificial vision systems. This sensing and processing technology is capable of very high speed throughput, because it does not rely on sensing and processing sequences of frames, and because it allows for complex hierarchically structured neuro-cortical-like layers for sophisticated processing. The paper describes briefly cortex-like spike event vision processing principles, and the AER (Address Event Representation) technique used in hardware spiking systems. In this paper we present a simulation AER tool that we have developed entirely in Visual C++ 6.0. We have validated it using real AER stimulus and comparing the outputs with real outputs obtained from AER-based devices. With this tool we can predict the eventual performance of AER-based systems, before the technology becomes mature enough to allow such large systems.This work was supported in part by grant TEC-2006-11730-C03-01 (Samanta2) from the Spanish Ministry of Eduation and Science and grant P06-TIC-01417 (Brain System) from the Andalusian regional government. JAPC was supported by a doctoral scholarship as part of research project Brain System.Peer Reviewe

Spike-based convolutional network for real-time processing

In this paper we propose the first bio-inspired six layer convolutional network (ConvNet) non-frame based that can be implemented with already physically available spike-based electronic devices. The system was designed to recognize people in three different positions: standing, lying or up-side down. The inputs were spikes obtained with a motion retina chip. We provide simulation results showing recognition delays of 16 milliseconds from stimulus onset (time-to-first spike) with a recognition rate of 94%. The weight sharing property in ConvNets and the use of AER protocol allow a great reduction in the number of both trainable parameters and connections (only 748 trainable parameters and 123 connections in our AER system (out of 506998 connections that would be required in a frame-based implementation).Peer Reviewe

On neuromorphic spiking architectures for asynchronous STDP memristive systems

Neuromorphic circuits and systems techniques have great potential for exploiting novel nanotechnology devices, which suffer from great parametric spread and high defect rate. In this paper we explore some potential ways of building neural network systems for sophisticated pattern recognition tasks using memristors. We will focus on spiking signal coding because of its energy and information coding efficiency, and concentrate on Convolutional Neural Networks because of their good scaling behavior, both in terms of number of synapses and temporal processing delay. We propose asynchronous architectures that exploit memristive synapses with specially designed neurons that allow for arbitrary scalability as well as STDP learning. We present some behavioral simulation results for small neural arrays using electrical circuit simulators, and system level spike processing results on human detection using a custom made event based simulator.Peer Reviewe