What's in a Sign? Trademark Law and Economic Theory

Abstract: The aim of this paper is to summarise the extant theory as it relates to the economics of trademark, and to give some suggestions for further research with reference to distinct streams of literature. The proposed line of study inevitably looks at the complex relationship between signs and economics. Trademark is a sign introduced to remedy a market failure. It facilitates purchase decisions by indicating the provenance of the goods, so that consumers can identify specific quality attributes deriving from their own, or others', past experience. Trademark holders, on their part, have an incentive to invest in quality because they will be able to reap the benefits in terms of reputation. In other words, trademark law becomes an economic device which, opportunely designed, can produce incentives for maximising market efficiency. This role must, of course, be recognised, as a vast body of literature has done, with its many positive economic consequences. Nevertheless, trademark appears to have additional economic effects that should be properly recognized: it can determine the promotion of market power and the emergence of rent-seeking behaviours. It gives birth to an idiosyncratic economics of signs where very strong protection tends to be assured, even though the welfare effects are as yet poorly understood. In this domain much remains to be done and the challenge to researchers is open

A Fully Programmable eFPGA-Augmented SoC for Smart-Power Applications

This paper proposes a reconfigurable System-on-Chip (SoC) for Smart-Power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications, featuring digital elaboration with small computational load, at a lower power consumption and higher responsiveness compared to processor-based implementation. Added value of the proposed system is that the whole digital system is synthesizable, since also the eFPGA is based on a soft-core approach. In the paper we discuss the application domain and present the results of integrating an eFPGA with a computational capability of 481K equivalent gates in the STMicroelectronics 0.13 \u3bcm Bipolar, CMOS, DMOS (BCD) Smart-Power technology featuring only four metal layers. As expected, eFPGA integration in the SoCs introduces a significant area-overhead (about 20\uf725% ), but has a straightforward benefit in terms of energy consumption reduction compared to processor-based implementations. On average, based on our analysis, the energy gain achievable in this scenario can be quantified in a couple of orders of magnitude

Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this per- formance/costs challenge is given by customizable multiprocessor system-on-chips. The approach proposed in this paper leads to the customization of multi/many processor system-on-chip at two levels of abstraction: 1) customization through application- specific hardware accelerators implemented on configurable datapath that can target three kinds of structured application- specific integrated circuit technologies: metal, via, and runtime programmable and 2) customization of the architectural para- meters of the platform. The proposed platform is equipped with a design framework that assists the user in the high-level design- space exploration of signal processing applications described using the Open Computing Language (OpenCL) language. A peculiar added value of the flow is to support the migration of OpenCL kernels and tasks into pipelined hardware accelerators described using a C-level language. The platform is able to provide an average performance of 90 GOPS on a set of reference signal processing applications, and an average computational energy efficiency of 130 GOPS/W in its metal-programmable configuration. This result shows the benefits in terms of energy efficiency of hardware customization applied to multiprocessor systems with respect to many core devices such as general- purpose graphic processing units, able to provide on average 2.5 GOPS/W for the applications under analysis

Input/Output pad for direct contact and contactless testing

Non-contact probing can provide an important contribution for testing complex Systems-on-a-Chip (SoC), Systems-in-a-Package (SiP) and Through-Silicon-Vias (TSV) interconnections. This paper demonstrates the feasibility of wireless testing by capacitive coupling between a cantilever probe card and a pad. In particular a scheme of an I/O pad suitable for both contact and contactless probing is proposed