Dataflow/Actor-Oriented language for the design of complex signal processing systems

Signal processing algorithms become more and more complex and the algorithm architecture adaptation and design processes cannot any longer rely only on the intuition of the designers to build efficient systems. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. This paper presents a new framework which allows the specification, design, simulation and implementation of a system operating at a higher level of abstraction compared to current approaches. The framework is base on the usage of a new actor/dataflow oriented language called CAL. Such language has been specifically designed for modelling complex signal processing systems. CAL data flow models expose the intrinsic concurrency of the algorithms by employing the notions of actor programming and dataflow. Concurrency and parallelism are very important aspects of embedded system design as we enter in the multicore era. The design framework is composed by a simulation platform and by Cal2C and CAL2HDL code generators. This paper described in details the principles on which such code generators are based and shows how efficient software (C) and hardware (VHDL and Verilog) code can be generated by appropriate CAL models. Results on a real design case, a MPEG-4 Simple Profile decoder, show that systems obtained with the hardware code generator outperform the hand written VHDL version both in terms of performance and resource usage. Concerning the C code generator results, the results show that the synthesized C-software mapped on a SystemC scheduler platform, is much faster than the simulated CAL dataflow program and approaches handwritten C versions

OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

This paper presents the OpenDF framework and recalls that dataflow programming was once invented to address the problem of parallel computing. We discuss the problems with an imperative style, von Neumann programs, and present what we believe are the advantages of using a dataflow programming model. The CAL actor language is briefly presented and its role in the ISO/MPEG standard is discussed. The Dataflow Interchange Format (DIF) and related tools can be used for analysis of actors and networks, demonstrating the advantages of a dataflow approach. Finally, an overview of a case study implementing an MPEG-4 decoder is given

Recent Advances in Literature Based Discovery

Literature Based Discovery (LBD) is a process that searches for hidden and important connections among information embedded in published literature. Employing techniques from Information Retrieval and Natural Language Processing, LBD has potential for widespread application yet is currently implemented primarily in the medical domain. This article examines several published LBD systems, comparing their descriptions of domain and input data, techniques to locate important concepts from text, models of discovery, experimental results, visualizations, and evaluation of the results. Since there is no comprehensive “gold standard, ” or consistent formal evaluation methodology for LBD systems, the development and usage of effective metrics for such systems is also discussed, providing several options. Also, since LBD is currently often time-intensive, requiring human input at one or more points, a fully-automated system will enhance the efficiency of the process. Therefore, this article considers methods for automated systems based on data mining

Reconfigurable media coding: self-describing multimedia bitstreams

The development of MP3 and JPEG sparked an explosion in digital content on the internet. These early encoding formats have since been joined by many others, including Quicktime, Ogg, MPEG-2 and MPEG-4, which poses an escalating challenge to vendors wishing to develop devices that interoperate with as much content as possible. This paper presents aspects of Reconfigurable Media Coding (RMC), a project currently underway at MPEG to define a self-describing bitstream format. In other words, an RMC bitstream contains metadata to assemble a decoder from a fundamental building-blocks, as well as a schema that describes the syntax of the content data, and how it may be parsed. RMC makes it easy to extend (reconfigure) existing codecs, for example adding error resilience or new chroma-subsampling profiles, or to build entirely new codecs. This paper addresses the bitstream syntax component of RMC, validating the approach by applying it to the recent MPEG-4 Video simple profile coder

Growth of thin film organic crystals with strong nonlinearity for on-chip second-order nonlinear optics

info:eu-repo/semantics/publishe

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

This paper proposes a new design methodology to partition streaming applications onto a multi clock domain architecture. The objective is to save power by running different parts of the application at the lowest possible clock frequency that will not violate the throughput requirements. The solution involves partitioning the application into an appropriate number of clock domains, and then assigning each of those domains a clock frequency. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and initial experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder implemented in a FPGA platform