Detector Technologies for CLIC

The Compact Linear Collider (CLIC) is a high-energy high-luminosity linear electron-positron collider under development. It is foreseen to be built and operated in three stages, at centre-of-mass energies of 380 GeV, 1.5 TeV and 3 TeV, respectively. It offers a rich physics program including direct searches as well as the probing of new physics through a broad set of precision measurements of Standard Model processes, particularly in the Higgs-boson and top-quark sectors. The precision required for such measurements and the specific conditions imposed by the beam dimensions and time structure put strict requirements on the detector design and technology. This includes low-mass vertexing and tracking systems with small cells, highly granular imaging calorimeters, as well as a precise hit-time resolution and power-pulsed operation for all subsystems. A conceptual design for the CLIC detector system was published in 2012. Since then, ambitious R&D programmes for silicon vertex and tracking detectors, as well as for calorimeters have been pursued within the CLICdp, CALICE and FCAL collaborations, addressing the challenging detector requirements with innovative technologies. This report introduces the experimental environment and detector requirements at CLIC and reviews the current status and future plans for detector technology R&D.Comment: 152 pages, 116 figures; published as CERN Yellow Report Monograph Vol. 1/2019; corresponding editors: Dominik Dannheim, Katja Kr\"uger, Aharon Levy, Andreas N\"urnberg, Eva Sickin

Assessment and Characterization of Stress Induced by Via-First TSV Technology

Through silicon via (TSV) is a key enabling technology for 3D stacking. One of the main concerns regarding the TSV introduction inside the IC fabrication is the resulting stress buildup in the silicon substrate that may induce warpage or expansion at the wafer level, strain and crystalline defects in the neighboring silicon of the TSV, and finally can impact the performance and reliability of the CMOS devices as well. Polysilicon, tungsten, and copper are the three main conductors that are currently considered for TSV fabrication. In the first part of this paper, the different factors that contribute to the stress in these three TSV types, including the geometry, the materials, and the process, will be reviewed. After bonding on a temporary carrier and thinning of the substrate to expose the via, the stress built up during the fabrication of the TSV can be also revealed by the expansion of the silicon membrane. We present thermomechanical FEM simulations and compare them with the experimental findings. We also present some characterizations of silicon defects by chemical revelation around the TSV structures. For characterization of the stress in TSV structures, different techniques as EBSD, microRaman, and XRD are presented. Finally, we conclude that with the optimization of some key processing steps, the stress induced in via-first technology may be acceptable for IC integration.</jats:p

Mars Microphone Testing and LIBS Acoustic Characterisation for the Mars 2020 Rover

International audienceResults of the SuperCam LIBS-Mars Microphone system in the Mars environment will be presented, including LIBS acoustic emission from martian soil analogs