2,614 research outputs found
Hardware proofs using EHDM and the RSRE verification methodology
Examined is a methodology for hardware verification developed by Royal Signals and Radar Establishment (RSRE) in the context of the SRI International's Enhanced Hierarchical Design Methodology (EHDM) specification/verification system. The methodology utilizes a four-level specification hierarchy with the following levels: functional level, finite automata model, block model, and circuit level. The properties of a level are proved as theorems in the level below it. This methodology is applied to a 6-bit counter problem and is critically examined. The specifications are written in EHDM's specification language, Extended Special, and the proofs are improving both the RSRE methodology and the EHDM system
Analysis of minimization algorithms for multiple-valued programmable logic arrays
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Proceedings of the 18th International Symposium on Multiple-Valued Logic, May 1988, pp. 226-236We compare the performance of three heuristic algorithms [3,6,13] for the minimization of
sum-of-products expressions realized by the newly
developed multiplevalued programmable logic arrays [9]. Heuristic methods are important because exact minimization is extremely time consuming. We compare the heuristics to the exact solution, showing that heuristic methods are reasonably close to minimal. We use as a basis of comparison the average number of product terms over a set of randomly generated functions. All three heuristics produce nearly the same average number of product terms. Although the averages are close, there is surprisingly little overlap among the set of functions where the best realization is achieved. Thus, there is a benefit to applying different heuristics and then choosing the best realization
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions
Because most practical logic design algorithms produce irredundant sum-of-products (ISOP) expressions, the understanding of ISOPs is crucial. We show a class of functions for which Morreale-Minato's ISOP generation algorithm produces worst ISOPs (WSOP), ISOPs with the most product terms. We show this class has the property that the ratio of the number of products in the WSOP to the number in the minimum ISOP (MSOP) is arbitrarily large when the number of variables is unbounded. The ramifications of this are significant; care must be exercised in designing algorithms that produce ISOPs. We also show that 2/sup n-1/ is a firm upper bound on the number of product terms in any ISOP for switching functions on n variables, answering a question that has been open for 30 years. We show experimental data and extend our results to functions of multiple-valued variables
Analysis of input and output configurations for use in four-valued programmable logic arrays
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Proceedings of the IEE-E: Computers and Digital Techniques, Vol. 134, No. 4, pp. 168-176, July 1987As in binary, a multiple-valued programmable logic array (PLA) realises a sum-of-products, expression specified by the user. However, in multiple-valued logic, there are many more operations than in binary, and an important question is the choice of operations with provides the greatest number of functions for a given chip area. In this paper, we analyse various PLA configurations using operations realised in the peristaltic multiple-valued CCD technology. We compare a multiple-valued CCD PLA implementation with four other proposed designs and show that there is a significant different in chip area required to realise the same set of functions. The basis of comparison is the set of 4-valued unary functions
A minimization algorithm for non-concurrent PLA's
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.International Journal of Electronics, Vol. 73, No. 6, Dec. 1992, pp. 1113-1119In the design of certain self-checking programmable logic arrays (PLAs), at most one line is activated in the AND plane, such as PLAs are termed non-concurrent. A heuristic algorithm for the minimization of non-concurrent PLAs is presented. It operates on two adjacent cubes, replacing them by one, two, and sometimes more than two cubes. The algorithm produces the best solutions known so far
A heat quench algorithm for the minimization of multiple-valued programmable logic arrays
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Computer and Electrical Engineering Journal, Vol. 22, No. 2, 1996, pp. 103-107, 1996imulated annealing has been used extensively to solve combinatorial problems. Although
it does not guarantee optimum results, results are often optimum or near optimum. The primary
disadvantage is slow speed. It has been suggested [1] that quenching (rapid cooling) yields results that are
far from optimum. We challenge this perception by showing a context in which quenching yields good
solutions with good computation speeds. In this paper, we present an algorithm in which quenching is
combined with rapid heating. We have successfully applied this algorithm to the multiple-valued logic
minimization problem. Our results suggest that this algorithm holds promise for problems where moves
exist that leave the cost of the current solution unchanged.
Key words: Multiple-valued logic, logic minimization, simulated annealing, heat quench, heuristic
Multiple-valued operations with universal literals
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.Proceedings of the 24th International Symposium on Multiple-Valued Logic, May 1994, pp. 73-79, 1993We propose the use of universal literals as a means of
reducing the cost of multiple-valued circuits. A universal
literal is any function on one variable. The target
architecture is a sum-of-products structure, where sum is
the truncated sum and product terms consist of the
minimum of universal literals. A significant cost
reduction is demonstrated over the conventional window
literal. The proposed synthesis method starts with a sum-
of products expression. Simplification occurs as pairs of
product terms are merged and reshaped. We show under
what conditions such operations can be applied
EVMDD-based analysis and diagnosis methods of multi-state systems with multi-state components
A multi-state system with multi-state components is a model of systems, where performance,
capacity, or reliability levels of the systems are represented as states. It usually has more than
two states, and thus can be considered as a multi-valued function, called a structure function.
Since many structure functions are monotone increasing, their multi-state systems can be
represented compactly by edge-valued multi-valued decision diagrams (EVMDDs). This paper presents
an analysis method of multi-state systems with multi-state components using EVMDDs. Experimental
results show that, by using EVMDDs, structure functions can be represented more compactly than
existing methods using ordinary MDDs. Further, EVMDDs yield comparable computation time for
system analysis. This paper also proposes a new diagnosis method using EVMDDs, and shows that the
proposed method can infer the most probable causes for system failures more efficiently than conventional methods based on Bayesian networks.Japan Society for the Promotion of ScienceMinistry of Education, Culture, Sports, Science and Technology (MEXT)Hiroshima City UniversityGrant-in Aid No. 2500050 (MEXT)Grant no. 0206 (HCU)Grant in Aid for Scientific Research (JSPS
A PVS Graph Theory Library
This paper documents the NASA Langley PVS graph theory library. The library provides fundamental definitions for graphs, subgraphs, walks, paths, subgraphs generated by walks, trees, cycles, degree, separating sets, and four notions of connectedness. Theorems provided include Ramsey's and Menger's and the equivalence of all four notions of connectedness
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