Wafer-level integration of on-chip antennas and RF passives using high-resistivity polysilicon substrate technology

High-resistivity polycrystalline silicon (HRPS) wafers are utilized as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components (e.g. large inductors) in wafer-level chip-scale packages (WLCSP). Sandwiching of HRPS and silicon wafers enables to integrate large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to singlecrystalline silicon.Philips Semiconductors and Philips Research in the context of the Philips Associate Centre at DIMES (PACD); Fundação para a Ciência e Tecnologia (FCT) (SFRH/BD/4717/2001, POCTI/ESE/38468/2001, FEDER), and the EC (project Blue Whale IST-2000-10036)

High-resistivity polycrystalline silicon as RF substrate in wafer-level packaging

High-resistivity polycrystalline silicon (HRPS) is presented as a novel low-cost and low-loss substrate for radio-frequency (RF) passive components in wafer-level packaging and integrated passive networks. A record quality factor (Q¼11; 1 GHz; 34 nH) and very low loss (0.65 dB=cm; 17 GHz) are demonstrated for inductors and coplanar waveguides, respectively, on HRPS.EC project Bluewhale (IST-2000-10036), and of the Portugese Foundation for Science and Technology (SFRH=BD=4717=2001, POCTI=ESE=38468=2001, FEDER)

Characterization of high-resistivity polycrystalline silicon substrates for wafer-level packaging and integration of RF passives

High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate for radio-frequency (RF) passive components in wafer-level packaging (WLP) and integrated passive networks. A record quality factor (Q=11; 1 GHz; 34 nH) and very low loss (0.65 dB/cm; 17 GHz) are demonstrated for inductors and coplanar wave guides, respectively. The waferlevel packaging solution is based on an adhesive bonding of a passive HRPS wafer to an active silicon IC wafer, where the HRPS wafer serves as a mechanical carrier and vertical spacer. This enables integration of large RF passives with a vertical spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to the single-crystalline silicon.Philips Semiconductors and Philips Research in the context of the Philips Associate Centre at DIMES (PACD); Fundação para a Ciência e Tecnogia (FCT) (SFRH/BD/4717/2001, POCTI/ESE/38468/2001, FEDER), and the European Commission (project Blue Whale IST-2000-3006)

Wafer-level chip-scale packaging for low-end RF products

This paper gives a short overview of waferlevel chip-scale packaging technology and analyses its added value in the packaging of RF ICs. Particularly, the possibilities of substrate crosstalk suppression by substrate thinning and trenching together with embedding of rf passives (inductors, antennas) are addressed. The Shellcasetype wafer-level packaging solution is used as a study case presenting its fabrication aspects and its potential for RF IC packaging.Philips Semiconductors and Philips Research, Fundação para a Ciência e Tecnologia (FCT) - (SFRH/BD/4717/2001, POCTI/ESE/38468/2001), European Union under FP5 for the project Blue Whale (IST-2000-10036)