SCALE memory subsystem

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (leaf 79).Dynamic Random Access Memory (DRAM) is consuming an ever-increasing portion of a system's energy budget as advances are made in low-power processors. In order to reduce these energy costs, modern DRAM chips implement low-power operating modes that significantly reduce energy consumption but introduce a performance penalty. This thesis discusses the design and evaluation of an energy-aware DRAM subsystem which leverages the power-saving features of modern DRAM chips while maintaining acceptable system performance. As this subsystem may employ a number of different system policies, the effect of each of these policies on system energy and performance is evaluated. The optimal overall policy configurations in terms of energy, delay, and energy-delay product are presented and evaluated. The configuration which minimizes the energy-delay product demonstrates average energy savings of 41.8% as compared to the high-performance configuration, while only introducing an 8.8% performance degradation.by Brian S. Pharris.M.Eng

The Vector-Thread Architecture

The vector-thread (VT) architectural paradigm unifies the vector and multithreaded compute models. The VT abstraction provides the programmer with a control processor and a vector of virtual processors (VPs). The control processor can use vector-fetch commands to broadcast instructions to all the VPs or each VP can use thread-fetches to direct its own control flow. A seamless intermixing of the vector and threaded control mechanisms allows a VT architecture to flexibly and compactly encode application parallelism and locality, and a VT machine exploits these to improve performance and efficiency. We present SCALE, an instantiation of the VT architecture designed for low-power and high-performance embedded systems. We evaluate the SCALE prototype design using detailed simulation of a broad range of embedded applications and show that its performance is competitive with larger and more complex processors. 1

Reibung, Schmierung und Verschleiss

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