Mobility Measurement in Nanowires Based on Magnetic Field-Induced Current Splitting Method in H-Shape Devices

This work investigates a new method to measure mobility in nanowires. Based on a simple analytical approach and numerical simulations, we bring evidence that the traditional technique of Hall voltage measurement in low dimensional structures such as nanowires may generate large errors, while being challenging from a technological aspect. Here, we propose to extract the drift mobility in nanowires by measuring a variation of the electric current due to the presence of a magnetic field, in a specific nanowire network topology. This method overcomes the limitations inherent to the standard Hall effect technique and might open the way to a more precise and simple measurement of mobility in nanowires, still a matter of intensive research

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ~400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated

Local stressors to accommodate 1.2 to 5.6 GPa uniaxial tensile stress in suspended gate-all-around Si nanowire nMOSFETs by elastic local buckling

In this paper, we demonstrate the integration of local oxidation and metal-gate strain technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 μm long suspended Si nanowire MOSFETs, the highest process-based stress record in MOSFETs until now, by elastic local buckling. Significant stress level modulation in the channel from 1.2 to 5.6 GPa on a single wafer is demonstrated for the first time by varying the NW width. The GAA Si NW MOSFET with 5.6 GPa uniaxial tensile stress is characterized and the electron mobility enhancement is reported

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier lowering is investigated with respect to key technological parameters, namely, the doping level in the channel, the minimum slit width, and the effective radius of the slit. This work could serve as a guideline for technology optimization, design and scaling of JL VeSFETs