The Effect of Retro-Cueing on an ERP Marker of VSTM Maintenance

Previous research has found that Contralateral Delay Activity (CDA) is correlated with the number of items maintained in Visual Short Term Memory from one visual field (VF) (Vogel & Machizawa, 2004). CDA is usually elicited by a to-be-remembered array after a prospective cue (pro-cue) signalling the relevant side of the visual display, and is interpreted as a putative electrophysiological signature of WM maintenance. Attention can also be directed to the contents of VSTM, after the presentation of a visual array, using a retroactive cue (retro-cue) (Nobre, Griffin, & Rao, 2008). Because retro-cueing directs attention within a memory trace, potentially reducing the load of items to be maintained, we hypothesised that this would significantly attenuate the CDA. Participants were initially presented with a spatial pro-cue which reduced the number of to-be-remembered items to one side. After a delay, a memory array of either four (low load) or eight (high load) items was displayed. A retro-cue then cued participants to one location within the relevant VF, further reducing the load of to-be-remembered items; or provided no information, requiring participants to hold all items in the relevant VF. At the end of the trial, participants performed a same/different judgement on a test stimulus. Retro-cues significantly improved VSTM performance. Unexpectedly, the CDA was found to be abolished by the presentation of both spatially predictive and neutral cues, independently of the VSTM load participants had to maintain

Updated constraints on Georgi-Machacek model, and its electroweak phase transition and associated gravitational waves

With theoretical constraints such as perturbative unitarity and vacuum stability conditions and updated experimental data of Higgs measurements and direct searches for exotic scalars at the LHC, we perform an updated scan of the allowed parameter space of the Georgi-Machacek (GM) model. With the refined global fit, we examine the allowed parameter space for inducing strong first-order electroweak phase transitions (EWPTs) and find only the one-step phase transition is phenomenologically viable. Based upon the result, we study the associated gravitational wave (GW) signals and find most of which can be detected by several proposed experiments. We also make predictions on processes that may serve as promising probes to the GM model in the near future at the LHC, including the di-Higgs productions and several exotic scalar production channels.Comment: 42 pages, 11 figures, 9 table

High Performance Post-Quantum Key Exchange on FPGAs

Lattice-based cryptography is a highly potential candidate that protects against the threat of quantum attack. At Usenix Security 2016, Alkim, Ducas, Pöpplemann, and Schwabe proposed a post-quantum key exchange scheme called NewHope, based on a variant of lattice problem, the ring-learning-with-errors (RLWE) problem. In this work, we propose a high performance hardware architecture for NewHope. Our implementation requires 6,680 slices, 9,412 FFs, 18,756 LUTs, 8 DSPs and 14 BRAMs on Xilinx Zynq-7000 equipped with 28mm Artix-7 7020 FPGA. In our hardware design of NewHope key exchange, the three phases of key exchange costs 51.9, 78.6 and 21.1 microseconds, respectively. It achieves more than 4.8 times better in terms of area-time product comparing to previous results of hardware implementation of NewHope-Simple from Oder and Güneysu at Latincrypt 2017

Small Odd Prime Field Multivariate PKCs

We show that Multivariate Public Key Cryptosystems (MPKCs) over fields of small odd prime characteristic, say 31, can be highly efficient. Indeed, at the same design security of $2^{80}$ under the best known attacks, odd-char MPKC is generally faster than prior MPKCs over \GF{2^k}, which are in turn faster than ``traditional\u27\u27 alternatives. This seemingly counter-intuitive feat is accomplished by exploiting the comparative over-abundance of small integer arithmetic resources in commodity hardware, here embodied by SSE2 or more advanced special multimedia instructions on modern x86-compatible CPUs. We explain our implementation techniques and design choices in implementing our chosen MPKC instances modulo small a odd prime. The same techniques are also applicable in modern FPGAs which often contains a large number of multipliers