Lower power by voltage stacking: a fine-grained system design approach

Stacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and VDD, and the memory "on top of it" between VDD and 2VDD, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in "stacked mode" of 96%

Floorplan and placement methodology for improved energy reduction in stacked power-domain design

Energy and battery lifetime constraints are critical challenges to IC designs. Stacked power-domain implementation, which stacks voltage domains in a design, can effectively improve the power delivery efficiency and thus improve battery lifetime. However, such an approach requires balanced current between different domains across multiple operating scenarios. Furthermore, level shifter insertion (together with shifters' delay impacts), along with placement constraints imposed by power domain regions, can incur power and area penalties. To our knowledge, no existing work performs sub-block-level partitioning optimization for stacked-domain designs. In this paper, we present an optimization framework for stacked-domain designs. Based on an initial placement solution, we apply a flow-based partitioning that is aware of multiple operating scenarios, cell placement, and timing-critical paths to partition cells into two power domains with balanced current and minimized number of inserted level shifters. We further propose heuristics to define regions for each power domain so as to minimize placement perturbation, as well as a dynamic programming-based method to minimize the area cost of power domain generation. In an updated floorplan, we perform matching-based optimization to insert level shifters with minimized wirelength penalty. Overall, our method achieves more than ∼10% and 3X battery lifetime improvements in function and sleep modes, respectively

Lower power by voltage stacking:a fine-grained system design approach

\u3cp\u3eStacking voltage domains on top of each other is a design approach that is getting the attention of engineering communities due to the implicit high efficiency of the power delivery. Previous works have shown voltage stacking at the core level only. In this paper we present a more involved approach required to deploy voltage stacking not at the core level but at the IP level of a complex microcontroller. Our demonstrator chip features an ARM Cortex M0+ platform with an on-chip switched-capacitor voltage regulator. We chose to place the standard logic in one voltage domain between ground and V\u3csub\u3eDD\u3c/sub\u3e, and the memory on top of it between V\u3csub\u3eDD\u3c/sub\u3e and 2V\u3csub\u3eDD\u3c/sub\u3e, creating in this way a voltage stacked system. We further present silicon measurements that include a measured peak power efficiency in stacked mode of 96%.\u3c/p\u3

A low-power microcontroller in a 40-nm CMOS using charge recycling

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to VDD, while its 4-kB ROM and the 16-kB SRAM are powered from VDD to 2 VDD. Since the memory and logic will, in general, draw different supply currents, the midrail VDD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and VDD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV

A microcontroller with 96% power-conversion efficiency using stacked voltage domains

This paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR). By using voltage stacking the test chip achieves state-of-the-art (96%) power-conversion efficiency and observed power savings run from 23% to 63% depending upon the payload current, while supply voltage variations are reduced from 5.6mV to 3.8mV (RMS)

Investigaciones en administración y políticas públicas

El Estado aborda dicha planificación definiendo los fundamentos ideológicos- conceptuales en los cuales se enmarcará el plan, coordinando y dirigiendo el proceso y las acciones a seguir y convocando a los diversos actores de la sociedad. El objetivo del presente artículo es dar cuenta de dicha planificación estratégica, entendida como un proceso de elaboración de una política pública. Para ello se presentarán en un primer apartado las nuevas modalidades de gestión vinculadas a las nuevas demandas de las sociedades actuales en continuo crecimiento y transformación. Dentro de estas nuevas modalidades, se puede encontrar a la planificación estratégica, entendida como tecnología de gestión integrada por un conjunto de instrumentos que permiten mejorar las capacidades delosequipos de gestión en orden a realizar las operaciones gerenciales necesarias para generar mayores niveles de eficiencia yeficaci

A low-power microcontroller in a 40-nm CMOS using charge recycling

\u3cp\u3eA 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to V\u3csub\u3eDD\u3c/sub\u3e, while its 4-kB ROM and the 16-kB SRAM are powered from V\u3csub\u3eDD\u3c/sub\u3e to 2 V\u3csub\u3eDD\u3c/sub\u3e. Since the memory and logic will, in general, draw different supply currents, the midrail V\u3csub\u3eDD\u3c/sub\u3e is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and V\u3csub\u3eDD\u3c/sub\u3e. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.\u3c/p\u3

Evaluation of the Digene Hybrid Capture II Assay with the Rapid Capture System for Detection of Chlamydia trachomatis and Neisseria gonorrhoeae

Screening for chlamydial and gonococcal infection has been strongly recommended for all sexually active women under the age of 26. Advances in the ability to detect infection by nucleic acid detection techniques have improved access to screening methods in routine clinical practices. To meet the increasing demand for testing, a high-throughput system is desirable. We evaluated the performance of the Hybrid Capture 2 CT/GC (HC2) assay with the Digene Rapid Capture System (HC2-RCS). The results of HC2-RCS for endocervical samples from 330 women were compared to those of culture and the COBAS Amplicor PCR. For detection of chlamydial infection, HC2-RCS had a sensitivity and a specificity similar to those of PCR (P > 0.5) and an improved sensitivity compared to that of culture (P = 0.007). For identification of gonococcal infections, all assays performed similarly (P > 0.5). The performance of HC2-RCS was also compared to that of the manual HC2 format (HC2-M) with these samples and with 911 endocervical samples collected previously. The performance of HC2-RCS was equivalent to that of HC2-M; the overall concordance rates for the detection of chlamydia and gonorrhea were 99.7% (κ = 0.97) and 99.8% (κ = 0.97), respectively. When the HC2 assay was performed with a semiautomated system application designed for high throughput, it demonstrated high sensitivity and a high specificity for detection of both Chlamydia trachomatis and Neisseria gonorrhoeae

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to VDD, while its 4-kB ROM and the 16-kB SRAM are powered from VDD to 2 VDD. Since the memory and logic will, in general, draw different supply currents, the midrail VDD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and VDD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.Accepted Author ManuscriptMicroelectronic

A microcontroller with 96% power-conversion efficiency using stacked voltage domains

\u3cp\u3eThis paper presents a CMOS 40nm microcontroller where for the first time, stacked voltage domains are used. The system features an ARM Cortex M0+ processor, 4kB ROM, 16kB SRAM, peripherals, and an on-chip switched-capacitor voltage regulator (SCVR). By using voltage stacking the test chip achieves state-of-the-art (96%) power-conversion efficiency and observed power savings run from 23% to 63% depending upon the payload current, while supply voltage variations are reduced from 5.6mV to 3.8mV (RMS).\u3c/p\u3