Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures &gt;225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm , on-resistance of 200 kΩ , and a via pitch of 0.4 μm , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.QC 20180412</p

Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory

Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 ∘C

Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems

Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.Tredimensionell (3D) integration av mikro- och nano-elektromekaniska system (MEMS/NEMS) med integrerade kretsar (ICs) är en ny teknik som erbjuder stora fördelar jämfört med konventionell mikroelektronik. MEMS och NEMS används oftast som sensorer och aktuatorer då de möjliggör många funktioner som inte kan uppnås med vanliga ICs.3D-integration av NEMS och ICs bidrar även till mindre dimensioner, ökade prestanda och mindre energiförbrukning av elektriska komponenter. Den nuvarande tekniken för complementary metal-oxide-semicondictor (CMOS) närmar sig de fundamentala gränserna vilket drastiskt begränsar utvecklingsmöjligheten för mikroelektronik och medför slutet på Moores lag. Därför har 3D-integration identifierats som en lovande teknik för att kunna driva vidare utvecklingen för framtidens elektriska komponenter.I denna avhandling framläggs en omfattande fabrikationsmetodik för heterogen 3D-integration av NEMS ovanpå CMOS-kretsar. Heterogen integration betyder att både NEMS- och CMOS-komponenter byggs på separata substrat för att sedan förenas på ett enda substrat. Denna teknik tillåter full processfrihet för tillverkning av NEMS-komponenter och garanterar kompatibilitet med standardiserade CMOS-fabrikationsprocesser.I den första delen av avhandlingen beskrivs en metod för att sammanfoga två halvledarskivor med en extremt tunn adhesiv polymer. Denna metod demonstreras för 3D-integration av NEMS- och CMOS-komponenter. Den andra delen introducerar ett nytt koncept för NEM-switchar och dess användning i NEM-switch-baserade mikrodatorchip. Den tredje delen presenterar två olika inkapslingsmetoder för MEMS och NEMS. Den ena metoden fokuserar på hermetisk vakuuminkapsling medan den andra metoden beskriver en lågkostnadsstrategi för inkapsling av optiska komponenter. Slutligen i den fjärde delen presenteras en ny fabrikationsteknik för så kallade ”through silicon vias” (TSVs) baserad på magnetisk självmontering av nickeltråd på mikrometerskala.20170519</p

High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires

This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.QC 20161019</p

Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint

Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 ̊C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as 2.6×10-2 mbar. Based on this value, the leak rate is calculated to be smaller than 3.6×10-16 mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for 5.2 μm-high Cu sealing rings with widths down to 8 μm. The reported method is potentially compatible with complementary metaloxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates.QC 20170516When citing this work, please cite the original published paper.</p

Narrow footprint copper sealing rings for low-temperature hermetic wafer-level packaging

This paper reports a narrow footprint sealing ring design for low-temperature, hermetic, and mechanically stable wafer-level packaging. Copper (Cu) sealing rings that are as narrow as 8 μm successfully seal the enclosed cavities on the wafers after bonding at a temperature of 250 °C. Different sealing structure designs are evaluated and demonstrate excellent hermeticity after 3 months of storage in ambient atmosphere. A leak rate of better than 3.6×10'16 mbarL/s is deduced based on results from residual gas analysis measurements. The sealing yield after wafer bonding is found to be not limited by the Cu sealing ring width but by a maximum acceptable wafer-to-wafer misalignment.QC 20171215</p

Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires

Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (&gt;20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.QC 20120827</p

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors