6,497 research outputs found
An ART1 microchip and its use in multi-ART1 systems
Recently, a real-time clustering microchip neural engine based on the ART1 architecture has been reported. Such chip is able to cluster 100-b patterns into up to 18 categories at a speed of 1.8 μs per pattern. However, that chip rendered an extremely high silicon area consumption of 1 cm2, and consequently an extremely low yield of 6%. Redundant circuit techniques can be introduced to improve yield performance at the cost of further increasing chip size. In this paper we present an improved ART1 chip prototype based on a different approach to implement the most area consuming circuit elements of the first prototype: an array of several thousand current sources which have to match within a precision of around 1%. Such achievement was possible after a careful transistor mismatch characterization of the fabrication process (ES2-1.0 μm CMOS). A new prototype chip has been fabricated which can cluster 50-b input patterns into up to ten categories. The chip has 15 times less area, shows a yield performance of 98%, and presents the same precision and speed than the previous prototype. Due to its higher robustness multichip systems are easily assembled. As a demonstration we show results of a two-chip ART1 system, and of an ARTMAP system made of two ART1 chips and an extra interfacing chip
A modified ART 1 algorithm more suitable for VLSI implementations
This paper presents a modification to the original ART 1 algorithm (Carpenter and Grossberg, 1987a, A massively parallel architecture for a self-organizing neural pattern recognition machine, Computer Vision, Graphics, and Image Processing, 37, 54–115) that is conceptually similar, can be implemented in hardware with less sophisticated building blocks, and maintains the computational capabilities of the originally proposed algorithm. This modified ART 1 algorithm (which we will call here ART 1m) is the result of hardware motivated simplifications investigated during the design of an actual ART 1 chip [Serrano-Gotarredona et al., 1994, Proc. 1994 IEEE Int. Conf. Neural Networks (Vol. 3, pp. 1912–1916); Serrano-Gotarredona and Linares-Barranco, 1996, IEEE Trans. VLSI Systems, (in press)]. The purpose of this paper is simply to justify theoretically that the modified algorithm preserves the computational properties of the original one and to study the difference in behavior between the two approaches
On the design and characterization of femtoampere current-mode circuits
In this paper, we show and validate a reliable circuit design technique based on source voltage shifting for current-mode signal processing down to femtoamperes. The technique involves specific-current extractors and logarithmic current splitters for obtaining on-chip subpicoampere currents. It also uses a special on-chip sawtooth oscillator to monitor and measure currents down to a few femtoamperes. This way, subpicoampere currents are characterized without driving them off chip and requiring expensive instrumentation with complicated low leakage setups. A special current mirror is also introduced for reliably replicating such low currents. As an example, a simple log-domain first-order low-pass filter is Implemented that uses a 100-fF capacitor and a 3.5-fA bias current to achieve a cutoff frequency of 0.5 Hz. A technique for characterizing noise at these currents is also described and verified. Finally, transistor mismatch measurements are provided and discussed. Experimental measurements are shown throughout the paper, obtained from prototypes fabricated in the AMS 0.35-μm three-metal two-poly standard CMOS process.Ministerio de Ciencia y Tecnología TIC-1999-0446-C02-02, FIT-070000-2001-0859, TIC-2000-0406-P4-05, TIC-2002-10878-EEuropean Union IST-2001-3412
Log-domain implementation of complex dynamics reaction-diffusion neural networks
In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that implements the spatially discretized version of the selected reaction-diffusion equation. The logarithmic compression of the state variables allows several decades of variation of these state variables within subthreshold operation of the MOS transistors. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. As a demonstrator, we have designed a chip containing a linear array of ten second-order dynamics coupled cells. Using this hardware, we have experimentally reproduced two complex spatio-temporal phenomena: the propagation of travelling waves and of trigger waves, as well as isolated oscillatory cells.Gobierno de España TIC1999-0446-C02-02Office of Naval Research (USA
A high-precision current-mode WTA-MAX circuit with multichip capability
This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented
Evaluation of a permeability-porosity relationship in a low permeability creeping material using a single transient test
A method is presented for the evaluation of the permeability-porosity
relationship in a low-permeability porous material using the results of a
single transient test. This method accounts for both elastic and non-elastic
deformations of the sample during the test and is applied to a hardened class G
oil well cement paste. An initial hydrostatic undrained loading is applied to
the sample. The generated excess pore pressure is then released at one end of
the sample while monitoring the pore pressure at the other end and the radial
strain in the middle of the sample during the dissipation of the pore pressure.
These measurements are back analysed to evaluate the permeability and its
evolution with porosity change. The effect of creep of the sample during the
test on the measured pore pressure and volume change is taken into account in
the analysis. This approach permits to calibrate a power law
permeability-porosity relationship for the tested hardened cement paste. The
porosity sensitivity exponent of the power-law is evaluated equal to 11 and is
shown to be mostly independent of the stress level and of the creep strains
7-decade tuning range CMOS OTA-C sinusoidal VCO
A new operational transconductance amplifier-capacitor (OTA-C) based sinusoidal voltage-controlled oscillator (VCO) has been designed and fabricated, the oscillation frequency of which can be tuned from 74 mHz to 1 MHz. The VCO uses a new OTA whose transconductance is adjusted by using a set of special current mirrors. These current mirrors operate in weak inversion and their gain can be controlled continuously through a gate voltage over many decades. This is the first report of such a wide tuning range for CMOS sinusoidal oscillators. Experimental results are provided
Effect of environmental variables on financial performance: the case of electrical industry
Nowadays, companies at the electrical industry have to meet numerous environmental requirements which involve a large increment in their costs. However, it is considered that these investments made by organizations may affect positively to their reputation and therefore to their profits. So the aim of this paper is to analyze the influence that some Environmental variables related to the emission and resource reductions have on the Financial Performance of the electrical firms through a data panel methodology. The sample was composed by 72 electrical companies over the world, during the period 2008-2010
Automatic Metadata Creation for Supporting Interoperability Levels of Spatial Data Infrastructures
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