Tests of Sapphire Crystals Produced with Different Growth Processes for Ultra-stable Microwave Oscillators

We present the characterization of 8-12 GHz whispering gallery mode resonators machined in high-quality sapphire crystals elaborated with different growth techniques. These microwave resonators are intended to constitute the reference frequency of ultra-stable Cryogenic Sapphire Oscillators. We conducted systematic tests near 4 K on these crystals to determine the unloaded Q-factor and the turnover temperature for whispering gallery modes in the 8-12 GHz frequency range. These characterizations show that high quality sapphire crystals elaborated with the Heat Exchange or the Kyropoulos growth technique are both suitable to meet a fractional frequency stability better than 1x10-15 for 1 s to 10.000 s integration times.Comment: 7 figure

S-ROGUE: Routing protocol for Unmanned Systems on the Surface

International audienceThe cooperation of heterogeneous unmanned systems , for instance, between aerial engines and terrestrial engines, relies on reliable communication. Data delivery is ensured by routing protocols, but traditional routing approaches, MANET and DTN, are not efficient in such networks. In this paper, we propose the S-ROGUE routing protocol combining the paradigms MANET and DTN and switching between them according to the network connectivity. On the one hand, the S-ROGUE MANET algorithm relies on a proactive approach and a novel metric to anticipate link disruptions and detect unidirectional links. On the other hand, the S-ROGUE DTN algorithm uses on a reinforcement learning technique to select the best routing action. It implements also a replication control and packet prioritization to improve routing performances. We lead a performance evaluation of S-ROGUE with similar routing protocols in realistic simulated environments and conclude that S-ROGUE has the best routing performance regardless the scenarios

Usines 3D. La simulation pour questionner les sources et les vestiges de l'histoire industrielle

Virtual retrospect est un colloque sur l'utilisation de la réalité virtuelle pour l'archéologie créé par Robert Vergnieux. Il est organisé par ArchéoVision (http://archeovision.cnrs.fr), la plateforme 3D de l'institut Ausonius (CNRS, Université de Bordeaux 3) et centre de ressource 3D du très grand équipement Adonis.International audienceUsines3D is a historical research program that explores issues of industrial spaces. At time, historical analysis of this program are based on a search tool using 3D restitution technologies and linking data through interoperable databases.Usines3D est un programme de recherche en histoire moderne et histoire contemporaine qui explore les questions de la restitution d'espaces industriels. Les analyses historiques s'appuient sur un outil de recherche qui utilise les techniques de la restitution 3D et la mise en relation de données au sein de bases de données interopérables (voir http://www.usines3d.fr)

On the imaging of electron transport in semiconductor quantum structures by scanning-gate microscopy: successes and limitations

This paper presents a brief review of scanning-gate microscopy applied to the imaging of electron transport in buried semiconductor quantum structures. After an introduction to the technique and to some of its practical issues, we summarise a selection of its successful achievements found in the literature, including our own research. The latter focuses on the imaging of GaInAs-based quantum rings both in the low magnetic field Aharonov-Bohm regime and in the high-field quantum Hall regime. Based on our own experience, we then discuss in detail some of the limitations of scanning-gate microscopy. These include possible tip induced artefacts, effects of a large bias applied to the scanning tip, as well as consequences of unwanted charge traps on the conductance maps. We emphasize how special care must be paid in interpreting these scanning-gate images.Comment: Special issue on (nano)characterization of semiconductor materials and structure

A New Development Framework for Multi-Core Processor based Smart-Camera Implementations

International audienceThe exponential evolution of the smart camera processing performances is directly linked to the improvements on hardware processing elements. Nowadays, high processing performances can be reached considering hardware targets which enables a high level of task parallelism to be implemented. Highly regular tasks are good candidate for a reconfigurable logic implementation and less regular parts of the algorithm could be described on the processor. Meanwhile the prototyping time is related to the selected target and the associated development methodology. The implementation on reconfigurable logic is highly efficient in exploiting the intrinsic task parallelism nevertheless can be time consuming using traditional methodology (i.e. Hardware Language Description). Several approaches can be considered to decrease the proto-typing time and to conserve high processing performances for instance implementation based on: • heterogeneous architectures [1] that mixed reconfig-urable logic (i.e. FPGA) and embedded processor, • high-level abstraction description and the associated fast prototyping tools [2][3][4], • multi-core processor architectures such as Digital Signal Processors (DSP), Graphic Processor Units (GPU) or even Generic Purpose Processor (GPP). In this paper, we propose to focus on implementation based on GPP due to the emergence of new generation of low-cost multi-core processors which enables high processing performances to be reached and therefore to match with some constraints of complex image-processing algorithms. The key idea of this development is to be able to propose fast prototyping using a low-cost smart camera based on this kind of target. Hence, we have developed a new framework dedicated to multi-core processor associated with an image sensor. The framework aims to offer a high degree of flexibility for managing the tasks and the memory allocation. Hence, the framework enables the priority and the allocation of each task to be controlled. Each task (or binary) is independent in terms of execution nevertheless it can be linked and controlled using a higher hierarchy level binary. The image acquisition task can be completely independent from the other processing tasks. One processor's core can even be dedicated to the acquisition task to guarantee a constant input data-flow to the image processing tasks. The data exchange is defined in POSIX, each binary can be therefore coded differently (for instance in C or C++, or in another languages) and offer a relative Operating System (OS) compatibility. The memory management enables a sequence of images to be automatically stored and a simultaneous access to be granted for several processings. The framework includes an interface dedicated to the management of the tasks: the user can add or suppress a binary during the runtime, logs or processing results can be visualised for each task

La banque de données Médoc mécanisation de la France xixe-xxe siècles

Définition d'une problématique : la mécanisation envisagée comme l'un des processus centraux de l'industrialisation La mécanisation est l'un des aspects clés pour comprendre le processus d'ensemble de l'industrialisation. Cette notion recouvre en réalité deux dynamiques à la fois conjointes et distinctes. D'une part, la mécanisation comme substitution toujours plus étendue du machinisme au travail manuel dans la sphère de la production. De l'autre, comme extension continue des applications de..