Technique de réduction adaptative de l'espace de recherche pour les méthodes d'optimisation par recherche locale

National audienceWhen applied to practical problems, tuning parameters of optimization methods can be a critical problem for engineer users. In this article we suggest a novel approach to consider constrained optimization problems. Its principal caracteristics are flexibility, adaptativity and user friendship. Indeed constraints are totally separated from the cost function. It allows to be directly coupled with any local search algorithm in order to explore the solution space which is reduced in an adaptive manner. Its implementation is compared to other existing methods with discrete and continuous classical problems. Results show that the method approaches the best results thus offering a good trade-off between flexibity and quality for the solutions

Technique de réduction d'ordonnancements hors-ligne pour applications embarquées à contraintes temps réel

National audienceThis article presents an optimization technic of static real-time scheduling. The goal is to minimize the size in embedded memory of the scheduling tables defined at compile-time. This compression of the results of classical scheduling algorithms exploits Idle times in multiprocessors systems in order to identify cyclic patterns. The proposed approach is based on a compact description format near to the Synchronous Data Flow Graphs (SDFG). When applied to our case studies, the average compression rate of our technic is near to 70% of the initial schedule size

Méthodes d'optimisation pour le partitionnement logiciel/matériel de systèmes à description multi-modèles

La complexité des systèmes embarqués, l'hétérogénéité de leur spécification et la nécessité de les concevoir et de les produire à moindre coût motivent l'introduction d'outils d'aide à la conception au niveau système. Cette thèse traite du partitionnement logiciel/matériel, qui consiste à définir l'architecture du système (processeurs, circuits dédiés, mémoires, ...) et à affecter les traitements aux processeurs et aux circuits. Ce problème est formulé comme un problème d'optimisation dont l'objectif est de minimiser le coût global du système. En utilisant une méthode de recherche locale et en construisant un environnement permettant d'intégrer facilement de nouveaux modèles de traitement et de composants de l'architecture, on montre qu'il est possible d'obtenir des solutions proches de l'optimum pour des spécifications hétérogènes (DFG, flots de données synchrones). L'efficacité est obtenue en accélérant une version rapide du recuit simulé et en la rendant plus facile à utiliser.The complexity of embedded systems, the heterogeneity of their specification and the need to design and manufacture them at the lowest cost motivate the introduction of CAD tools at the system level. This thesis deals specifically with hardware/software partitioning, i.e. defining the architecture of the system (processors, ASICs, memory, etc.) and assigning the computations to the processors and dedicated ICs. This problem is formulated as an optimization problem whose objective is the minimization of the global cost of the system. By using a local search method and by building an environment that enables easy integration of new models of computation and of novel architectural components, we show how to reach solutions close to the global optimum for heterogeneously specified systems (DFG, SDF, etc.). Efficiency is achieved by starting with a fast version of simulated annealing, improving further on its speed and reducing parameter tuning to a minimum.EVRY-BU (912282101) / SudocVILLEURBANNE-DOC'INSA LYON (692662301) / SudocSudocFranceF

Generation of static tables in embedded memory with dense scheduling

International audienc

Decision Guide Environment for Design Space Exploration

International audienceIn current embedded system design practice, only few architectural solutions and mappings of the functionalities of a system on the architecture's components are examined. This paper presents an optimization-based method and the associated tool developed to help designers take architectural decisions. The principle of this approach is to efficiently explore the design space and to dynamically provide the user with the capabilities to visualize the evolution of selected criteria. The first objective is solved by developing an enhanced version of the adaptive simulated annealing algorithm. Since the method is iterative, multiple solutions may be examined and the tool lets the user stop exploration at any time, tune parameters and select solutions. Moreover we present an approach for systems whose functionalities are specified by means of multiple models of computation, in order to handle descriptions of digital signal applications at several levels of detail. The tool has been applied to a motion detection application in order to determine architectural parameters

Design Space Exploration for Dynamically Reconfigurable Architectures

International audienceBy incorporating reconfigurable hardware in embedded system architectures it has become easier to satisfy the performance constraints of demanding applications while lowering system cost. In order to evaluate the performance of a candidate architecture, the nodes (tasks) of the data flow graphs that describe an application must be assigned to the computing resources of the architecture: programmable processors and reconfigurable FPGA, whose run-time reconfiguration capabilities must be exploited. In this paper we present a novel design exploration tool - based on a local search algorithm with global convergence properties - which simultaneously explores choices for computing resources, assignments of nodes to these resources, task schedules on the programmable processors and context definitions for the reconfigurable circuits. The tool finds a solution that minimizes system cost while meeting the performance constraints; more precisely it lets the designer select the quality of the optimization (hence its computing time) and finds accordingly a solution with close-to-minimal cost

Object Detection with Spiking Neural Networks on Automotive Event Data

voir aussi ANR DeepSee (ANR-17-CE24-0036)International audienceAutomotive embedded algorithms have very high constraints in terms of latency, accuracy and power consumption. In this work, we propose to train spiking neural networks (SNNs) directly on data coming from event cameras to design fast and efficient automotive embedded applications. Indeed, SNNs are more biologically realistic neural networks where neurons communicate using discrete and asynchronous spikes, a naturally energy-efficient and hardware friendly operating mode. Event data, which are binary and sparse in space and time, are therefore the ideal input for spiking neural networks. But to date, their performance was insufficient for automotive real-world problems,such as detecting complex objects in an uncontrolled environment. To address this issue, we took advantage of the latest advancements in matter of spike backpropagation - surrogate gradient learning, parametric LIF, SpikingJelly framework - and of our new voxel cube event encoding to train 4 different SNNs based on popular deep learning networks: SqueezeNet, VGG, MobileNet, and DenseNet. As a result, we managed to increase the size and the complexity of SNNs usually considered in the literature. In this paper, we conducted experiments ontwo automotive event datasets, establishing new state-of-the-art classification results for spiking neural networks. Based on these results, we combined our SNNs with SSD to propose the first spiking neural networks capable of performing object detection on the complex GEN1 Automotive Detection event dataset

Simulation de haut niveau de systèmes d'exploitations distribués pour l'exploration matérielle et logicielle d'architectures multi-noeuds hétérogènes

Concevoir un système embarqué implique de trouver un compromis algorithme/architecture en fonction des contraintes temps-réel. Thèse : pour un MPSoC et plus particulièrement avec les circuits reconfigurables qui permettent de modifier le support d'exécution en cours de fonctionnement, l'évaluation préalable des comportements fluctuants d'un système réactif devient une nécessité. Il faut donc valider par simulation (de haut niveau) tout en permettant l'exploration de l'espace de conception architectural, matériel et logiciel. Le point de vue du gestionnaire de la plateforme est choisi pour explorer à haut niveau les réactions du système aux choix de partitionnement et surtout l'influence de l'algorithmique des services du système d'exploitation et de leurs implémentations possibles. Pour cela un modèle de services d'OS modulaire permet de simuler fonctionnellement et conjointement, en SystemC, le matériel, les tâches logicielles et le système d'exploitation, répartis sur plusieurs nœuds d'exécution hétérogènes communicants. Le modèle a permis d'évaluer l'architecture temps-réel idéale d'une application dynamique de vision robotique conjointement à l'exploration des services de gestion de zone reconfigurable modélisé. Par ailleurs, ce modèle d'OS à été intégré dans un simulateur de MPSoC hétérogène d'une puissance estimé à un Tera opérations par seconde.Designing an embedded system implies to look for the right algorithm/architecture compromise depending on the real-time constraints. For MPSoC an especially with reconfigurable devices which enable to modify the running executing support, the preliminary evaluation of the variable behaviors of a reactive system becomes necessary.This could be done by a high level simulation allowing to explore the architectural design space, hardware and software. The platform manager point of view is used to explore the systems reactions to the partitioning choices and also the influence of the various algorithms and the impact of implementations of the operating system's services refined in hardware or software. For that, a SystemC model composed of modular OS services allow to jointly and functionally simulate hardware, software tasks and the operating system, distributed on heterogeneous communicating execution nodes. To evaluate the perfect real-time reconfigurable architecture of a dynamical robot vision application, we explored its partitioning and the useful OS services accordingly. This model has been integrated in a big simulator of an heterogeneous chip designed to provide a Tera operations per second power.CERGY PONTOISE-Bib. electronique (951279901) / SudocSudocFranceF

MicroAI

<h2>MicroAI is deprecated and superseded by Qualia</h2><p>Please check the new Qualia repositories out at <a href="https://github.com/orgs/LEAT-EDGE/repositories">https://github.com/orgs/LEAT-EDGE/repositories</a> and the documentation at <a href="https://leat-edge.github.io/qualia/">https://leat-edge.github.io/qualia/</a> .</p><p> </p><p> </p><p>MicroAI is a software framework for end-to-end deep neural networks training, quantization and deployment onto embedded devices.</p><p>This framework is designed as an alternative to existing proprietary inference engines on microcontrollers. Our framework can be easily adjusted and/or extended for specific use cases. The training phase relies on Keras or PyTorch. Execution using single precision 32-bit floating-point as well as fixed-point on 8- and 16 bits integers are supported.</p><p> </p><p><a href="https://bitbucket.org/edge-team-leat/uca-ehar">https://bitbucket.org/edge-team-leat/uca-ehar</a></p>https://bitbucket.org/edge-team-leat/microai_publi