Piecewise contractions defined by iterated function systems

Let $\phi_1,\ldots,\phi_n:[0,1]\to (0,1)$ be Lipschitz contractions. Let $I=[0,1)$, $x_0=0$ and $x_n=1$. We prove that for Lebesgue almost every $(x_1,...,x_{n-1})$ satisfying $0<x_1<\cdots <x_{n-1}<1$, the piecewise contraction $f:I\to I$ defined by $x\in [x_{i-1},x_i)\mapsto \phi_i(x)$ is asymptotically periodic. More precisely, $f$ has at least one and at most $n$ periodic orbits and the $\omega$-limit set $\omega_f(x)$ is a periodic orbit of $f$ for every $x\in I$.Comment: 16 pages, two figure

Asymptotically periodic piecewise contractions of the interval

We consider the iterates of a generic injective piecewise contraction of the interval defined by a finite family of contractions. Let $\phi_i:[0,1]\to (0,1)$, $1\le i\le n$, be $C^2$-diffeomorphisms with $\sup_{x\in (0,1)} \vert D\phi_i(x)\vert<1$ whose images $\phi_1([0,1]), \ldots, \phi_n([0,1])$ are pairwise disjoint. Let $0<x_1<\cdots<x_{n-1}<1$ and let $I_1,\ldots, I_n$ be a partition of the interval $[0,1)$ into subintervals $I_i$ having interior $(x_{i-1},x_i)$, where $x_0=0$ and $x_n=1$. Let $f_{x_1,\ldots,x_{n-1}}$ be the map given by $x\mapsto \phi_i(x)$ if $x\in I_i$, for $1\le i\le n$. Among other results we prove that for Lebesgue almost every $(x_1,\ldots,x_{n-1})$, the piecewise contraction $f_{x_1,\ldots,x_{n-1}}$ is asymptotically periodic.Comment: 8 page

A multiplexed mixed-signal fuzzy architecture

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually oriented to fast low-power systems with low-medium complexity. The paper presents a strategy to preserve most of the advantages of an analog implementation, while allowing a notorious increment of the system complexity. Such strategy consists in implementing a reduced number of rules, those that really determine the output in a lattice controller, which we call analog core, then this core is dynamically programmed to perform the computation related to a specific rule set. The data to program the analog core are stored in a memory, and constitutes the whole knowledge base in a kind of virtual rule set. HSPICE simulations from an exemplary controller are shown to illustrate the viability of the proposal

Multiplexing architecture for mixed-signal CMOS fuzzy controllers

Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the advantages of an analogue implementation, while allowing a marked increment in system complexity, is presented.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

Neuro-fuzzy chip to handle complex tasks with analog performance

This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7μm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided

A mixed-signal fuzzy controller and its application to soft start of DC motors

Presents a mixed-signal fuzzy controller chip and its application to control of DC motors. The controller is based on a multiplexed architecture presented by the authors (1998), where building blocks are also described. We focus here on showing experimental results from an example implementation of this architecture as well as on illustrating its performance in an application that has been proposed and developed. The presented chip implements 64 rules, much more than the reported pure analog monolithic fuzzy controllers, while preserving most of their advantages. Specifically, the measured input-output delay is around 500 ns for a power consumption of 16 mW and the chip area (without pads) is 2.65 mm/sup 2/. In the presented application, sensed motor speed and current are the controller input, while it determines the proper duty cycle to a PWM control circuit for the DC-DC converter that powers the motor drive. Experimental results of this application are also presented.Comisión Interministerial de Ciencia y Tecnología TIC99-082

A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm single-poly technology. Measurements are given to demonstrate its performance. All the operations needed for fuzzy inference are realized on-chip using analog circuitry compatible with standard VLSI CMOS technologies. On-chip digital control and memory circuitry is also incorporated for programmability. The chip architecture and circuitry are based on our design methodology for neurofuzzy systems reported in [1]. A few architectural modifications are made to share circuitry among rules and, thus, obtain reduced area and power consumption. The chip parameters can be learned in situ, for operation in a changing environment, by using dedicated hardware-compatible learning algorithms [1][8

A Reuse-based framework for the design of analog and mixed-signal ICs

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits (ICs) under stringent time-to-market (TTM) requirements is lagging behind integration capacity, so far keeping pace with still valid Moore's Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools and design methodologies -and, possibly, a design paradigm shift-that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design has hindered a similar level of consensus and development. This paper presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the two first for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks. A case study and a functional silicon prototype demonstrate the validity of the paper's proposals.Ministerio de Educación y Ciencia TEC2004-0175

Geometrically-constrained, parasitic-aware synthesis of analog ICs

In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de Educación y Ciencia TEC2004-0175