Interactive Parallelization of Embedded Real-Time Applications Starting from Open-Source Scilab & Xcos

International audienceIn this paper, we introduce the workflow of interactive parallelization for optimizing embedded real-time applications for multicore architectures. In our approach, the real-time applications are written in the Scilab high-level mathematical & scientific programming language or with a Scilab Xcos block-diagram ap-proach. By using code generation and code parallelization technol-ogy combined with an interactive GUI, the end user can map appli-cations to the multicore processor iteratively. The approach is eval-uated on two use cases: (1) an image processing application written in Scilab and (2) an avionic system modeled in Xcos. Using the workflow, an end-to-end model-based approach targeting multicore processors is enabled resulting in a significant reduction in devel-opment effort and high application speedup. The workflow de-scribed in this paper is developed and tested within the EU-funded ARGO project focused on WCET-Aware Parallelization of Model-Based Applications for Heterogeneous Parallel Systems

A new approach for on-line placement on reconfigurable devices

By increasing the amount of resources on reconfigurable platforms with the abililty of partial reconfigurability, the issues of the management of these resources and their sharing among different tasks will become more of a concern. Online placement is one of these management issues that is investigated in this paper. Here we present a new approach for online placement of modules on reconfigurable devices, by managing the occupied space rather the free space on the device. Also an optimization of communication between running modules themselves and outside of the chip is proposed. The experimental results show a considerable decrease in communication and routing costs

Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware

The implementation of large linear control systems requires a high amount of digital signal processing. Here, we show that reconfigurable hardware allows the design of fast yet flexible control systems. After discussing the basic concepts for the design and implementation of digital controllers for mechatronic systems, a new general and automated design flow starting from a system of differential equations to application-specific hardware implementation is presented. The advances of reconfigurable hardware as a target technology for linear controllers is discussed. In a case study, we compare the new hardware approach for implementing linear controllers with a software implementation

Interactive Parallelization of Embedded Real-Time Applications Starting from Open-Source Scilab & Xcos

International audienceIn this paper, we introduce the workflow of interactive parallelization for optimizing embedded real-time applications for multicore architectures. In our approach, the real-time applications are written in the Scilab high-level mathematical & scientific programming language or with a Scilab Xcos block-diagram ap-proach. By using code generation and code parallelization technol-ogy combined with an interactive GUI, the end user can map appli-cations to the multicore processor iteratively. The approach is eval-uated on two use cases: (1) an image processing application written in Scilab and (2) an avionic system modeled in Xcos. Using the workflow, an end-to-end model-based approach targeting multicore processors is enabled resulting in a significant reduction in devel-opment effort and high application speedup. The workflow de-scribed in this paper is developed and tested within the EU-funded ARGO project focused on WCET-Aware Parallelization of Model-Based Applications for Heterogeneous Parallel Systems

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach

International audienceParallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project 1 provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach