56,785 research outputs found
Energy Model of Networks-on-Chip and a Bus
A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC link
Extended Abstract: Analysis of 1000 Arbiter PUF based RFID Tags
In this extended abstract a large-scale analysis of 4-
way Arbiter PUFs is performed with measurement results from
1000 RFID tags. Arbiter PUFs are one of the most important
building blocks in PUF-based protocols and have been the
subject of many papers. However, in the past often only software
simulations or a limited number of test chips were available for
analysis. Therefore, the goal of this work is to verify earlier
findings in regard to the uniqueness and reliability of Arbiter
PUFs by using a much larger measurement set. Furthermore, we
used machine learning algorithms to approximate and compare
the internal delay differences of the employed PUF. One of the
main research questions in this paper is to examine if any
“outliers” occurred, i.e., if some tags performed considerably
different. This might for example happen due to some unusual
manufacturing variations or faults. However, our findings are that
for all of the analyzed tags the parameters fell within the range
of a Gaussian distribution without significant outliers. Hence, our
results are indeed in line with the results of prior work
Trojans in Early Design Steps—An Emerging Threat
Hardware Trojans inserted by malicious foundries
during integrated circuit manufacturing have received substantial
attention in recent years. In this paper, we focus on a different
type of hardware Trojan threats: attacks in the early steps of
design process. We show that third-party intellectual property
cores and CAD tools constitute realistic attack surfaces and that
even system specification can be targeted by adversaries. We
discuss the devastating damage potential of such attacks, the
applicable countermeasures against them and their deficiencies
Development of non-linear finite element computer code
Recent work has shown that the use of separable symmetric functions of the principal stretches can adequately describe the response of certain propellant materials and, further, that a data reduction scheme gives a convenient way of obtaining the values of the functions from experimental data. Based on representation of the energy, a computational scheme was developed that allows finite element analysis of boundary value problems of arbitrary shape and loading. The computational procedure was implemental in a three-dimensional finite element code, TEXLESP-S, which is documented herein
ATP-dependent nucleosome disruption at a heat-shock promoter mediated by binding of GAGA transcription factor
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