77 research outputs found
A Large-Scale Industrial Case Study on Architecture-Based Software Reliability Analysis
AbstractβArchitecture-based software reliability analysis methods shall help software architects to identify critical software components and to quantify their influence on the system reliability. Although researchers have proposed more than 20 methods in this area, empirical case studies applying these methods on large-scale industrial systems are rare. The costs and benefits of these methods remain unknown. On this behalf, we have applied the Cheung method on the software architecture of an industrial control system from ABB consisting of more than 100 components organized in nine subsystems with more than three million lines of code. We used the Littlewood/Verrall model to estimate subsystems failure rates and logging data to derive subsystem transition probabilities. We constructed a discrete time Markov chain as an architectural model and conducted a sensitivity analysis. This paper summarizes our experiences and lessons learned. We found that architecture-based software reliability analysis is still difficult to apply and that more effective data collection techniques are required. Keywords-Software reliability growth, software architecture, Markov processes I
Π―Π·ΡΠΊ ΠΈ ΠΌΠΈΡΠΎΠ²Π°Ρ ΠΊΡΠ»ΡΡΡΡΠ°: Π²Π·Π³Π»ΡΠ΄ ΠΌΠΎΠ»ΠΎΠ΄ΡΡ ΠΈΡΡΠ»Π΅Π΄ΠΎΠ²Π°ΡΠ΅Π»Π΅ΠΉ. Π§. 1
ΠΠ°ΡΡΠΎΡΡΠΈΠΉ ΡΠ±ΠΎΡΠ½ΠΈΠΊ ΠΎΠ±ΡΠ΅Π΄ΠΈΠ½ΡΠ΅Ρ ΠΈΡΡΠ»Π΅Π΄ΠΎΠ²Π°ΡΠ΅Π»ΡΡΠΊΠΈΠ΅ ΠΏΡΠΎΠ΅ΠΊΡΡ Π°ΡΠΏΠΈΡΠ°Π½ΡΠΎΠ² ΠΈ ΠΏΡΠ΅ΠΏΠΎΠ΄Π°Π²Π°ΡΠ΅Π»Π΅ΠΉ ΡΠ·ΡΠΊΠΎΠ²ΡΡ
ΠΊΠ°ΡΠ΅Π΄Ρ ΠΈ ΡΠΎΠ΄Π΅ΡΠΆΠΈΡ ΠΌΠ°ΡΠ΅ΡΠΈΠ°Π»Ρ, ΠΏΡΠ΅Π΄ΡΡΠ°Π²Π»ΡΡΡΠΈΠ΅ ΡΠΈΡΠΎΠΊΠΈΠΉ ΠΊΡΡΠ³ Π½Π°ΡΡΠ½ΠΎ-ΡΡΠ΅Π±Π½ΡΡ
ΠΈΠ½ΡΠ΅ΡΠ΅ΡΠΎΠ² Π² ΠΏΠ°ΡΠ°Π΄ΠΈΠ³ΠΌΠ΅ ΡΠΎΠ²ΡΠ΅ΠΌΠ΅Π½Π½ΡΡ
Π³ΡΠΌΠ°Π½ΠΈΡΠ°ΡΠ½ΡΡ
Π·Π½Π°Π½ΠΈΠΉ, ΠΈ Π²ΠΊΠ»ΡΡΠ°Π΅Ρ, Π² ΠΎΡΠ½ΠΎΠ²Π½ΠΎΠΌ, Π²ΠΎΠΏΡΠΎΡΡ ΡΠ΅ΠΎΡΠΈΠΈ ΠΈ ΠΏΡΠ°ΠΊΡΠΈΠΊΠΈ ΠΏΡΠ΅ΠΏΠΎΠ΄Π°Π²Π°Π½ΠΈΡ ΠΈΠ½ΠΎΡΡΡΠ°Π½Π½ΡΡ
ΡΠ·ΡΠΊΠΎΠ². Π‘Π±ΠΎΡΠ½ΠΈΠΊ Π°Π΄ΡΠ΅ΡΠΎΠ²Π°Π½ Π°ΡΠΏΠΈΡΠ°Π½ΡΠ°ΠΌ ΠΈ ΠΏΡΠ΅ΠΏΠΎΠ΄Π°Π²Π°ΡΠ΅Π»ΡΠΌ, Π° ΡΠ°ΠΊΠΆΠ΅ Π²ΡΠ΅ΠΌ, ΠΊΠΎΠ³ΠΎ ΠΈΠ½ΡΠ΅ΡΠ΅ΡΡΠ΅Ρ ΡΠ΅ΠΎΡΠΈΡ ΠΈ ΠΌΠ΅ΡΠΎΠ΄ΠΈΠΊΠ° ΠΏΡΠΎΡΠ΅ΡΡΠΈΠΎΠ½Π°Π»ΡΠ½ΠΎΠ³ΠΎ ΠΎΠ±ΡΠ°Π·ΠΎΠ²Π°Π½ΠΈΡ, ΠΌΠ΅ΡΠΎΠ΄ΠΈΠΊΠ° ΠΎΠ±ΡΡΠ΅Π½ΠΈΡ ΠΈΠ½ΠΎΡΡΡΠ°Π½Π½ΡΠΌ ΡΠ·ΡΠΊΠ°ΠΌ, ΠΈΠ·ΡΡΠ΅Π½ΠΈΠ΅ ΡΠ·ΡΠΊΠΎΠ² Π² ΠΈΡ
Π²Π·Π°ΠΈΠΌΠΎΡΠ²ΡΠ·ΠΈ Ρ ΡΠΈΠ»ΠΎΡΠΎΡΠΈΠ΅ΠΉ, Π»ΠΈΡΠ΅ΡΠ°ΡΡΡΠΎΠΉ, ΠΈΡΡΠΎΡΠΈΠ΅ΠΉ ΠΈ ΠΊΡΠ»ΡΡΡΡΠΎΠΉ
ΠΠ»ΡΠ±ΠΎΠΊΠΎΠ΅ ΠΎΠ±ΠΎΠ³Π°ΡΠ΅Π½ΠΈΠ΅ ΠΊΠ°ΠΎΠ»ΠΈΠ½Π° Π’ΡΠ³Π°Π½ΡΠΊΠΎΠ³ΠΎ ΠΌΠ΅ΡΡΠΎΡΠΎΠΆΠ΄Π΅Π½ΠΈΡ
Effective Verification for Low-Level Software with Competing Interrupts
Interrupt-driven software is difficult to test and debug, especially when interrupts can be nested and subject
to priorities. Interrupts can arrive at arbitrary times, leading to an exponential blow-up in the number of
cases to consider. We present a new formal approach to verifying interrupt-driven software based on symbolic
execution. The approach leverages recent advances in the encoding of the execution traces of interacting,
concurrent threads. We assess the performance of our method on benchmarks drawn from embedded systems
code and device drivers, and experimentally compare it to conventional approaches that use source-to-source
transformations. Our results show that our method significantly outperforms these techniques. To the best
of our knowledge, our work is the first to demonstrate effective verification of low-level embedded software
with nested interrupt
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