Quantitative Measurements of FPGA Utility in Special and General Purpose Processors

We present experimental results on FPGA use in special and general purpose processors, using as case studies a computational accelerator for gene sequence analysis, an integer implementation of the DLX microprocessor, and a real-time signal processor for rocket telemetry. All these devices have been successfully prototyped, and are now completely functional. We present detailed analysis of our experience with FPGAs in these machines, describing savings in chip count, power consumption, area, and cost. For all quantities except cost, measured savings were typically an order of magnitude improvement over discrete IC implementations. 2 1.0 Introduction Recent work at the Thayer School of Engineering has investigated the use of FPGAs in a variety of digital systems. We present here our results on FPGA usage in three advanced designs: a special purpose processor for gene sequence analysis, known as the GSP, an implementation of Patterson and Hennessy's DLX 32-bit microprocessor architec..

Large Integer Multiplication on Hypercubes

Previous work has reported on the use of polynomial transforms to compute exact convolution and to perform multiplication of large integers on a massively parallel processor. We now present results of an improved technique, using the Fermat Number Transform. When the Fermat Number Transform was first proposed, word length constraints limited its effectiveness. Despite the development of multidimensional techniques to extend the length of the FNT, the relatively small word length of existing machines made the transform of little more than academic interest. The emergence of new computer architectures, however, has made the Fermat Number Transform more attractive. On machines like the Connection Machine, for example, we may implement the Fermat Number Transform without regard to word length considerations. We present a convolution algorithm on a massively parallel processor, based on the Fermat Number Transform. We present some examples of the tradeoffs between modulus, interprocessor co..

Large Integer Multiplication on Massively Parallel Processors

We present results of a technique for multiplying large integers using the Fermat Number Transform. When the Fermat Number Transform was first proposed, word length constraints limited its effectiveness. Despite the development of multidimensional techniques to extend the length of the FNT, the relatively small word length of existing machines made the transform of little more than academic interest. The emergence of new computer architectures, however, has made the Fermat Number Transform more attractive. On machines like the Connection Machine, for example, we may implement the Fermat Number Transform without regard to word length considerations. We present a convolution algorithm on a massively parallel processor, based on the Fermat Number Transform. We present some examples of the tradeoffs between modulus, interprocessor communication steps, and input size. We then discuss the application of this algorithm in the multiplication of large integers, and report performance results on..

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We report the results of a year-long experiment in the use of robots to teach computer science. Our data set compares results from over 800 students on identical tests from both robotics and nonrobotics-based laboratory sessions. We also examine the effectiveness of robots in encouraging students to select computer science or computer engineering as a field of study. Our results are negative: test scores were lower in the robotics sections than in the nonrobotics ones, nor did the use of robots have any measurable effect on students ’ choice of discipline. We believe the most significant factor that accounts for this is the lack of a simulator for our robotics programming system. Students in robotics sections must run and debug their programs on robots during assigned lab times, and are therefore deprived of both reflective time and the rapid compile-run-debug cycle outside of class that is an important part of the learning process. We discuss this and other issues, and suggest directions for future work

Calculating the FHT in Hardware

We have developed a parallel, pipelined architecture for calculating the Fast Hartley Transform. Hardware implementation of the FHT introduces two challenges: retrograde indexing and data scaling. We propose a novel addressing scheme that permits the fast computation of FHT butterflies, and describe a hardware implementation of conditional block floating point scaling that reduces error due to data growth with little extra cost. Simulations reveal a processor capable of transforming a 1K-point sequence in 170 microseconds using a 15.4 MHz clock