The Role of Frequency and Duty Cycle on the Gate Reliability of p-GaN HEMTs

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers

Exploration of Gate Trench Module for Vertical GaN devices

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported.Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020

Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices

Compact modeling of charge trapping processes in GaN transistors is of fundamental importance for advanced circuit design. The goal of this article is to propose a methodology for modeling the dynamic characteristics of GaN power HEMTs in the realistic case where trapping/detrapping kinetics are described by stretched exponentials, contrary to ideal pure exponentials, thus significantly improving the state of the art. The analysis is based on: 1) an accurate methodology for describing stretched-exponential transients and extracting the related parameters and 2) a novel compact modeling approach, where the stretched exponential behavior is reproduced via multiple RC networks, whose parameters are specifically tuned based on the results of 1). The developed compact model is then used to simulate the transient performance of the HEMT devices as a function of duty cycle and frequency, thus providing insight on the impact of traps during the realistic switching operatio

Schottky Gate Induced Threshold Voltage Instabilities in p-GaN Gate AlGaN/GaN HEMTs

We present detailed ON-state gate current characterization of Schottky gate p-GaN capped AlGaN/GaN high-electron-mobility transistors (HEMTs) on two distinct gate processes. The threshold voltage is monitored from $10~mathrm {mu } ext{s}$ up to 100 s under positive gate bias stress and during recovery. The threshold voltage stability is affected by the balance between hole and electron current in the gate stack. More specifically, devices with uniform hole conduction across the p-GaN gate area demonstrate stable threshold voltage behavior up to $V_{g}=5,mathrm {V}$ , whereas devices with a dominating gate perimeter electron conduction demonstrate larger instabilities. Finally, the threshold voltage stability during OFF-state pulsed stress is investigated and correlated to the excess gate-to-drain charge extracted from capacitance curves

Threshold Voltage Instability Mechanisms in p-GaN Gate AlGaN/GaN HEMTs

In this study, we propose a technique to evaluate the transient threshold voltage behavior of p-GaN capped AlGaN/GaN high-electron-mobility transistors (HEMTs). The threshold voltage is monitored from 10 \u3bcs to 100 s during positive gate bias stress. Technology computer-aided design (TCAD) simulations offer in-depth analysis of the different threshold voltage instability mechanisms: (i) electron trapping at the AlGaN/GaN interface, (ii) hole accumulation and trapping at the p-GaN/AlGaN interface and in the AlGaN barrier, respectively, and (iii) hole depletion of the p-GaN layer

Role of the AlGaN barrier on the long-term gate reliability of power HEMTs with p-GaN gate

Forward gate constant voltage stress (CVS) has been performed on GaN-on-Si (200 mm) HEMTs with p-GaN gate, controlled by a Schottky metal-retracted/p-GaN junction, processed by imec with different gate process splits. In particular, the adoption of devices with a different magnesium (Mg) concentration in the p-GaN layer, AlGaN barrier thickness and AlGaN aluminium percentage (Al%), allowed us to identify the degradation of the AlGaN barrier as responsible for time-dependent gate breakdown at room temperature. Lowering the Al% of the barrier and the Mg concentration of the p-GaN layer leads to a longer gate lifetime, while an optimum AlGaN barrier thickness is identified at given Al%