Template-based Fault Injection Analysis of Block Ciphers

We present the first template-based fault injection analysis of FPGA-based block cipher implementations. While template attacks have been a popular form of side-channel analysis in the cryptographic literature, the use of templates in the context of fault attacks has not yet been explored to the best of our knowledge. Our approach involves two phases. The first phase is a profiling phase where we build templates of the fault behavior of a cryptographic device for different secret key segments under different fault injection intensities. This is followed by a matching phase where we match the observed fault behavior of an identical but black-box device with the pre-built templates to retrieve the secret key. We present a generic treatment of our template-based fault attack approach for SPN block ciphers, and illustrate the same with case studies on a Xilinx Spartan-6 FPGA-based implementation of AES-128

Experimental observation of particle sedimentation in a horizontal annular pipe

The behavior of a suspension sedimenting in a horizontal annular pipe is experimentally studied. The suspension is made of oil and spherical beads with diameter 150-180 µm at concentration 0.5 %, and is placed in an annular cylinder space of inner and outer diameters of 90 and 140 mm, respectively, and a thickness of 20 mm. During the sedimentation process, images are recorded with a camera at 1 fps. The south pole area constitutes an area of particular focus, where a clear fluid layer of constant thickness forms along the internal radius. Various particle tracking and velocimetry techniques are used to generate velocity profiles and monitor individual and collective motion of particles within the cell, enabling the identification of 4 zones of distinct bead behaviors. This analysis gives us important information about particles movement within a suspension sedimenting in a horizontal annular pipe

DPA on quasi delay insensitive asynchronous circuits: concrete results

International audienceThis paper presents the first concrete results of Differential Power Analysis applied on secured Quasi Delay Insensitive asynchronous logic. In fact, the properties of QDI asynchronous circuits (1-of-N encoded data and four-phase handshake protocol) are exploited to improved chip resistance against power analysis. Different architectures and design styles were investigated and analyzed. Three different DES circuits have been designed and fabricated: two in asynchronous technology and one in synchronous to be used as a reference. The results obtained demonstrate that QDI asynchronous circuits significantly improve the DPA resistance. This study also enabled us to identify some limits i.e. residual sources of leakage, that will be addressed in future works