DPA on quasi delay insensitive asynchronous circuits: concrete results

Abstract

International audienceThis paper presents the first concrete results of Differential Power Analysis applied on secured Quasi Delay Insensitive asynchronous logic. In fact, the properties of QDI asynchronous circuits (1-of-N encoded data and four-phase handshake protocol) are exploited to improved chip resistance against power analysis. Different architectures and design styles were investigated and analyzed. Three different DES circuits have been designed and fabricated: two in asynchronous technology and one in synchronous to be used as a reference. The results obtained demonstrate that QDI asynchronous circuits significantly improve the DPA resistance. This study also enabled us to identify some limits i.e. residual sources of leakage, that will be addressed in future works