Si(100)-SiO2 interface properties following rapid thermal processing

An experimental examination of the properties of the Si(100)-SiO2 interface measured following rapid thermal processing (RTP) is presented. The interface properties have been examined using high frequency and quasi-static capacitance-voltage (CV) analysis of metal-oxide-silicon (MOS) capacitor structures immediately following either rapid thermal oxidation (RTO) or rapid thermal annealing (RTA). The experimental results reveal a characteristic peak in the CV response measured following dry RTO and RTA (T > 800 degreesC), as the Fermi level at the Si(100)-SiO2 interface approaches the conduction band edge. Analysis of the QSCV responses reveals a high interface state density across the energy gap following dry RTO and RTA processing, with a characteristic peak density in the range 5.5x10(12) to 1.7x10(13) cm(-2) eV(-1) located at approximately 0.85-0.88 eV above the valence band edge. When the background density of states for a hydrogen-passivated interface is subtracted, another peak of lower density (3x10(12) to 7x10(12) cm(-2) eV(-1)) is observed at approximately 0.25-0.33 eV above the valence band edge. The experimental results point to a common interface state defect present after processes involving rapid cooling (10(1)-10(2) degreesC/s) from a temperature of 800 degreesC or above, in a hydrogen free ambient. This work demonstrates that the interface states measured following RTP (T > 800 degreesC) are the net contribution of the P-b0/P-b1 silicon dangling bond defects for the oxidized Si(100) orientation. An important conclusion arising from this work is that the primary effect of an RTA in nitrogen (600-1050 degreesC) is to cause hydrogen desorption from pre-existing P-b0/P-b1 silicon dangling bond defects. The implications of this work to the study of the Si-SiO2 interface, and the technological implications for silicon based MOS processes, are briefly discussed. The significance of these new results to thin oxide growth and optimization by RTO are also considered

Effects of Heparin and Enoxaparin on APP Processing and Aβ Production in Primary Cortical Neurons from Tg2576 Mice

Alzheimer's disease (AD) is caused by accumulation of Aβ, which is produced through sequential cleavage of β-amyloid precursor protein (APP) by the β-site APP cleaving enzyme (BACE1) and γ-secretase. Enoxaparin, a low molecular weight form of the glycosaminoglycan (GAG) heparin, has been reported to lower Aβ plaque deposition and improve cognitive function in AD transgenic mice

Cereal Domestication and Evolution of Branching: Evidence for Soft Selection in the Tb1 Orthologue of Pearl Millet (Pennisetum glaucum [L.] R. Br.)

BACKGROUND: During the Neolithic revolution, early farmers altered plant development to domesticate crops. Similar traits were often selected independently in different wild species; yet the genetic basis of this parallel phenotypic evolution remains elusive. Plant architecture ranks among these target traits composing the domestication syndrome. We focused on the reduction of branching which occurred in several cereals, an adaptation known to rely on the major gene Teosinte-branched1 (Tb1) in maize. We investigate the role of the Tb1 orthologue (Pgtb1) in the domestication of pearl millet (Pennisetum glaucum), an African outcrossing cereal. METHODOLOGY/PRINCIPAL FINDINGS: Gene cloning, expression profiling, QTL mapping and molecular evolution analysis were combined in a comparative approach between pearl millet and maize. Our results in pearl millet support a role for PgTb1 in domestication despite important differences in the genetic basis of branching adaptation in that species compared to maize (e.g. weaker effects of PgTb1). Genetic maps suggest this pattern to be consistent in other cereals with reduced branching (e.g. sorghum, foxtail millet). Moreover, although the adaptive sites underlying domestication were not formerly identified, signatures of selection pointed to putative regulatory regions upstream of both Tb1 orthologues in maize and pearl millet. However, the signature of human selection in the pearl millet Tb1 is much weaker in pearl millet than in maize. CONCLUSIONS/SIGNIFICANCE: Our results suggest that some level of parallel evolution involved at least regions directly upstream of Tb1 for the domestication of pearl millet and maize. This was unanticipated given the multigenic basis of domestication traits and the divergence of wild progenitor species for over 30 million years prior to human selection. We also hypothesized that regular introgression of domestic pearl millet phenotypes by genes from the wild gene pool could explain why the selective sweep in pearl millet is softer than in maize

Toxic epidermal necrolysis and Stevens-Johnson syndrome

Toxic epidermal necrolysis (TEN) and Stevens Johnson Syndrome (SJS) are severe adverse cutaneous drug reactions that predominantly involve the skin and mucous membranes. Both are rare, with TEN and SJS affecting approximately 1or 2/1,000,000 annually, and are considered medical emergencies as they are potentially fatal. They are characterized by mucocutaneous tenderness and typically hemorrhagic erosions, erythema and more or less severe epidermal detachment presenting as blisters and areas of denuded skin. Currently, TEN and SJS are considered to be two ends of a spectrum of severe epidermolytic adverse cutaneous drug reactions, differing only by their extent of skin detachment. Drugs are assumed or identified as the main cause of SJS/TEN in most cases, but Mycoplasma pneumoniae and Herpes simplex virus infections are well documented causes alongside rare cases in which the aetiology remains unknown. Several drugs are at "high" risk of inducing TEN/SJS including: Allopurinol, Trimethoprim-sulfamethoxazole and other sulfonamide-antibiotics, aminopenicillins, cephalosporins, quinolones, carbamazepine, phenytoin, phenobarbital and NSAID's of the oxicam-type. Genetic susceptibility to SJS and TEN is likely as exemplified by the strong association observed in Han Chinese between a genetic marker, the human leukocyte antigen HLA-B*1502, and SJS induced by carbamazepine. Diagnosis relies mainly on clinical signs together with the histological analysis of a skin biopsy showing typical full-thickness epidermal necrolysis due to extensive keratinocyte apoptosis. Differential diagnosis includes linear IgA dermatosis and paraneoplastic pemphigus, pemphigus vulgaris and bullous pemphigoid, acute generalized exanthematous pustulosis (AGEP), disseminated fixed bullous drug eruption and staphyloccocal scalded skin syndrome (SSSS). Due to the high risk of mortality, management of patients with SJS/TEN requires rapid diagnosis, evaluation of the prognosis using SCORTEN, identification and interruption of the culprit drug, specialized supportive care ideally in an intensive care unit, and consideration of immunomodulating agents such as high-dose intravenous immunoglobulin therapy. SJS and TEN are severe and life-threatening. The average reported mortality rate of SJS is 1-5%, and of TEN is 25-35%; it can be even higher in elderly patients and those with a large surface area of epidermal detachment. More than 50% of patients surviving TEN suffer from long-term sequelae of the disease

Dependability analysis: a new application for run-time reconfiguration

ISBN: 0769519261The probability of faults, and especially transient faults, occurring in the field is increasing with the evolutions of the CMOS technologies. It becomes therefore crucial to predict the potential consequences of such faults on the applications. Fault injection techniques based on the high level descriptions of the circuits have been proposed for an early dependability analysis. In this paper, a new approach is proposed, based on emulation and run-time reconfiguration. Performance evaluations and practical experiments on a Virtex development board are reported

Using run-time reconfiguration for fault injection applications

International audienceIn this paper, approaches using run-time reconfiguration for fault injection in programmable systems are introduced. In FPGA-based systems an important characteristic is the time to reconfigure the hardware, including re-synthesis, place and route and finally bitstream downloading. Modifications can be carried out at "low-level", directly in the bitstream, so that re-synthesizing the description can be avoided to inject new faults. Moreover, with some FPGA families (e.g. Virtex or AT6000), it is possible to reconfigure the hardware partially at run-time. Important time-savings can be achieved when taking advantage of these features. These characteristics fit well to apply with fault injection where the injection necessitates the reconfiguration of only a few resources of the device with a few modifications. Time gains can be various depending on the number and kind of faults to be injected and the device used for the experiments. The experiments show that his approach could be several orders faster than the implementation using Compile-Time Reconfiguration

Using run-time reconfiguration for fault injection in hardware prototypes

International audienceIn this paper, a new methodology for the injection of single event upsets (SEU) in memory elements is introduced. SEUs in memory elements can occur due to many reasons (e.g. particle hits, radiation) and at any time. It becomes therefore important to examine the behaviour of circuits when an SEU occurs in them. Reconfigurable hardware (especially FPGAs) was shown to be suitable to emulate the behaviour of a logic design and to realise fault injection. The proposed methodology for SEU injection exploits FPGAs and, contrarily to the most common fault injection techniques, realises the injection directly in the reconfigurable hardware, taking advantage of run-time reconfiguration capabilities of the device. In this case, no modification of the initial design description is needed to inject a fault, that results in avoiding hardware overheads and specific synthesis, place and route phases

Using run-time reconfiguration for fault injection applications

The probability of faults occurring in the field increases with the evolution of the CMOS technologies. It becomes, therefore, increasingly important to analyze the potential consequences of such faults on the applications. Fault injection techniques have been used for years to validate the dependability level of circuits and systems, and approaches have been proposed to analyze very early in the design process the functional consequences of faults. These approaches are based on the high-level description of the circuit or system and classically use simulation. Recently, hardware emulation on FPGA-based systems has been proposed to accelerate the experiments; in that case, an important characteristic is the time to reconfigure the hardware, including re-synthesis, place and route, and bitstream downloading. In this paper, an alternative approach is proposed, based on hardware emulation and run-time reconfiguration. Fault injection is carried out by direct modifications in the bitstream, so that re-synthesizing the description can be avoided. Moreover, with some FPGA families (e.g., Virtex or AT6000), it is possible to reconfigure the hardware partially at run-time. Important time-savings can be achieved when taking advantage of these features, since the injection of a fault necessitates the reconfiguration of only a few resources of the device. The injection process is detailed for several types of faults and experimental results are discussed

Using run-time reconfiguration for fault injection in hardware prototypes

ISBN: 0769507190In this paper, approaches using run-time reconfiguration (RTR) for fault injection in programmable systems are introduced. In FPGA-based systems an important characteristic is the time to reconfigure the hardware. With novel FPGA families (e.g. Virtex, AT6000) it is possible to reconfigure the hardware partially in run-time. Important time-savings can be achieved when taking advantage of this characteristic for fault injection as only a small part of the device must be reconfigured

Evaluation of a software-based error detection technique by RT-level fault injection

International audienceThis paper discusses the efficiency of a software hardening technique when transient faults occur in the processor elements. Faults are injected in the RT-Level model of the processor, thus providing a more comprehensive view of the robustness compared with injections limited to the registers in the programmer model (e.g. injections based on an Instruction Set Simulator or using instructions of the processor to modify contents of registers)