Designing a Novel high-speed ternary-logic multiplier using GNRFET Technology

Abstract:This paper presents a novel design of a ternary multiplierbased on graphene nanoribbon field-effect transistor(GNRFET). GNRFET, as a new material with superiorphysical and electronic properties, can be a good choiceinstead of conventional devices such as metal–oxide–semiconductor field-effect transistor (MOSFET) andCNTFET. Moreover, multiple-valued logic (MVL) canhelp to reduce area and decrease the computational stepcompared with binary logic. We proposed a ternarymultiplier with the resistors to produce ternary logic. Theproposed multiplier performances are analyzed byevaluating the delay, power, and power-delay product(PDP), with 15 nm process technologies based onGNRFET. The simulation results with HSPICEdemonstrate that the proposed design frameworkoutperforms state-of-the-art designs in circuit parameters

The use of reversible logic gates in the design of residue number systems

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2k, 2p-1}. Modulo 2n-1, 2n, and 2n+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2n-1, 2n+k, 2n+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers

New method for congestion control in wireless sensor network using neural network

Research works related to wireless sensor networks have recently grown. There are hardware which can receive multimedia data from the environment. These networks should be able to deliver high quality multimedia data to the receiver. In this paper a new congestion method is introduced with such features as sensitivity to delay and its changes. A system is suggested in this work which uses neural networks for detecting congestion especially in wireless sensor networks, and prevents from failure and stops in the network services and detects source of congestion

A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set

The high dynamic range residue number system (RNS) five-moduli { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } has been recently introduced as an arithmetically balanced five-moduli set for computation-intensive applications on wide operands such as asymmetric cryptography algorithms. The previous dedicated design of RNS components for this moduli set is just an unsigned reverse converter. In order to utilize of the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } in applications handling with signed numbers, two important components are needed: Sign Detector and Signed Reverse Converter. However, having both of these components results in high hardware requirements which makes RNS impractical. This paper overcomes to this problem by designing a unified unit which can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors knowledge, this is the first attempt to design sign detector for a moduli set including 2n±3 moduli. In order to achieve a hardware-amenable design, we first improved the performance of the previous unsigned reverse converter for the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }. Then, we extract a sign detection method from the structure of the reverse converter. Finally, we make the unsigned reverse converter to sign converter through the use of the extracted sign signal from the reverse converter. The experimental results shown that the proposed multifunctional unit has relatively the same performance in terms of area, delay and power-consumption than the previous unsigned reverse converter for the set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } while it can perform two complex signed operations