Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron CMOS devices where serious degradation of reliability is expected. Therefore, a new design approach has been considered at low level of abstraction in order to implement robustness and faulttolerance into these devices. Moreover, fault tolerant properties of multi- layer feed-forward artificial neural networks have been demonstrated. Thus, we have implemented this concept at circuit-level, using spiking neurons. Using this approach, the NOT, NAND and NOR Boolean gates have been developed in the AMS 0.35 µm CMOS technology. A very straightforward mapping between the value of a neural weight and one physical parameter of the circuit has also been achieved. Furthermore, the logic gates have been simulated using SPICE corners analysis which emulates manufacturing variations which may cause circuit faults. Using this approach, it can be shown that fault-absorbing neural networks that operate as the desired function can be built

A Novel Analog CMOS Cellular Neural Network for Biologically-Inspired Walking Robot

Abstract-We propose a novel analog CMOS circuit that implements a class of cellular neural networks (CNNs) for biologically-inspired walking robots. Recently, a class of autonomous CNNs, so-called a reaction-diffusion (RD) CNN, has applied to locomotion control in robotics. We have introduced a novel RD-CNN, and implemented it as an analog CMOS circuit by using multiple-input floating-gate (MIFG) MOS FETs. As a result, the circuit can operate in voltage-mode. From the results on computer simulations, we have shown that the circuit has capability to generate stable rhythmic patterns for locomotion control in a quadruped walking robot

High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair

We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 M Omega by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-mu m 2P-4M CMOS process technology is described. The resistance was 13 M Omega for a tail current of 10 nA and 135 M Omega for 1 nA. The chip area was 105 mu m x 110 mu m. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area

Spiking neuron devices consisting of single-flux-quantum circuits

Single-flux-quantum (SFQ) circuits can be used for making spiking neuron devices, which are useful elements for constructing intelligent, brain-like computers. The device we propose is based on the leaky integrate-and-fire neuron (IFN) model and uses a SFQ pulse as an action signal or a spike of neurons. The operation of the neuron device is confirmed by computer simulator. It can operate with a short delay of 100 ps or less and is the highest-speed neuron device ever reported

A subthreshold MOS neuron circuit based on the Volterra system

We present an analog neuron circuit consisting of a small number of metal-oxide semiconductor (MOS) devices operating in their subthreshold region. The dynamics of the circuit were designed to be equivalent to the well-known Volterra system to facilitate developing the circuit for a particular application. We show that a simple nonlinear transformation of system variables in the Volterra system enables designing a neuron-like oscillator, which can produce sequences in time of identically shaped pulses (spikes) by using current-mode subthreshold MOS circuits. We present experimental results of the fabricated neuron circuits as well as an application in an inhibitory neural network, where the neurons compete with each other in the frequency and time domains

A1-μW 600-ppm/℃ Current Reference Circuit Consisting of Subthreshold CMOS Circuits

A low-power CMOS current reference circuit was developed using a 0.35-μm standard CMOS process technology. The circuit consists of MOSFET circuits operating in the subthreshold region and uses no resistors. It compensates for the temperature effect on mobility μ and threshold voltage V_[TH] of MOSFETs and generates a reference current that is insensitive to temperature and supply voltage. Theoretical analyses and experimental results showed that the circuit generates a stable reference current of 100 nA. The temperature coefficient of the current was 520 ppm/℃ at best and 600 ppm/℃ on average in the range of 0 ℃-80 ℃. The line regulation was 0.2%/V in a supply voltage range of 1.8-3 V. The power dissipation was 1μW, and the chip area was 0.015 mm2. Our circuit would be suitable for use in subthreshold-operated power-aware large-scale integrations

Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques

A voltage-controlled oscillator (VCO) tolerant to process variations at lower supply voltage was proposed. The circuit consists of an on-chip threshold-voltage-monitoring circuit, a current-source circuit, a body-biasing control circuit, and the delay cells of the VCO. Because variations in low-voltage VCO frequency are mainly determined by that of the current in delay cells. a current-compensation technique was adopted by using an on-chip threshold-voltage-monitoring circuit and body-biasing circuit techniques. Monte Carlo SPICE simulations demonstrated that variations in the oscillation frequency by using the proposed techniques were able to be suppressed about 65% at a I-V supply voltage, compared to frequencies with and without the techniques

Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits

A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-μm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits