Masking internal node logical faults and trojan circuits injections with using SAT solvers

We consider a combination circuit (the combinational part of a sequential circuit) and some nodes which faults are detected on the last stages of the circuit fabrication. Besides, injections of Trojan Circuits (TCs) in certain circuit lines may be detected. It is supposed that TC payload output is inserted into a line of combinational circuit C. In both cases circuit malfunction is connected with changing incompletely specified Boolean functions correlated with the corresponding fault nodes or the circuit lines. That is why masking (patch) circuit has to be an implementation of the correct incompletely specified Boolean functions system. This system is calculated with using SAT solver. Masking (patch) circuit inputs are connected with circuit C inputs and outputs are connected with nodes that are fed either by fault nodes or by circuit lines in that of which Trojan circuits are inserted. Experimental results are executed on circuits that behavior cannot be represented by ROBDDs because of their huge sizes. The results show that masking (patch) circuits may be essentially simpler than duplication

Algorithmic methods of inspection and diagnosis of discrete control devices and problems of inspectable design

Available from VNTIC / VNTIC - Scientific & Technical Information Centre of RussiaSIGLERURussian Federatio

Applying incompletely specified Boolean functions for patch circuit generation

We consider combination circuit C and some its nodes that faults are detected on the last stages of circuit fabrication. Besides, injections of Trojan Circuits (TCs) in certain circuit C lines may be also detected. (It is assumed that TC payload output is inserted into a line of a combinational circuit). In both cases circuit C improper functions are changed for incompletely specified Boolean functions correlated with the corresponding fault nodes or the circuit lines of correct circuit C. That is why masking of circuit faults and TCs injections may be reduced to implementation of a patch circuit that realizes the correct system of incompletely specified Boolean functions, in particular, depending on internal circuit C variables. The correct system is calculated with using SAT solver. Patch circuit inputs are connected with internal nodes of circuit C that precede both fault nodes and the lines. Patch circuit outputs are connected with nodes that are fed either by fault nodes or by circuit lines in which Trojan circuits are inserted. Experimental results are executed on ISCAS test circuits. The results show that patch circuits as a rule are simpler than duplication subcircuit with fault node as outputs and preceding nodes as inputs

A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test

Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of scan design is due to the scan multiplexers added to the inputs of every flip-flop. In today's very high speed designs with minimum possible combinational depth, the performance degradation caused by scan multiplexer has became magnified. Hence to maintain the circuit performance the timing overhead of scan design must be addressed. In this paper we propose a new scan flip-flop design that eliminates the performance overhead of serial scan. The proposed design removes the scan multiplexer off the functional path. The proposed design can help in improving the functional frequency of performance critical designs. Furthermore, the proposed design can be used as a common scan flip-flop in mixed mode scan test wherein it can be used as a serial scan cell as well as random access scan (RAS) cell

A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan

The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits

Multiple stuck-at fault testability analysis of ROBDD based combinational circuit design

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage

SAT solvers application of deriving all test pairs detecting robust testable PDFs

It is known that if we have set of test pairs of neighbor Boolean vectors for robust testable PDF for each path considered in the given circuit, we may derive test sequence for these faults consisting of fragments that are characterized by minimal length and minimal power consumption. Conventionally they try to find at least one test pair. It is possible to find all test pairs using operations on ROBDDs. In the frame of SAT technology it is possible to find products presenting test pairs one by one. It seemed that having got several products presenting test pairs we may derive rather high quality test sequence for the given set of circuit paths. New approach to deriving test pairs in the frame of SAT technology is suggested. The approach is based on deriving the combinational circuit that represents all test pairs. This circuit is constructed from the given combinational circuit and the chosen circuit path. The complexity of the obtained circuit practically coincides with the complexity of the given combinational circuit. Using this circuit we may obtain products representing test pairs one by one

Deriving approximate logic circuits for TMR technique

The Triple-Modular Redundancy (TMR) technique is one of the conventional approaches to provide reliable functioning of logic circuits. When using outsourcing, it is possible to inject a Trojan Circuit (TC) in the same line of each identical TMR module, and the TMR technique becomes vulnerable. It is necessary to withstand to vulnerability. One way of solving this problem is the application of two approximate logic circuits and one correct circuit that implements the proper functioning in the frame of the TMR technique. However, this approach, as a rule, generates an unprotected area in which a fault of one of the three circuits may be undetected. It is desirable to minimize this area. In this paper, approximate circuits are built based on deriving approximate systems of Boolean functions. These systems are then applied for an approximate circuit synthesis. The approach gives additional possibilities for cutting the unprotected area compared to the methods suggested before. Algorithms of deriving the approximate systems of the Boolean functions based on analysis of an irredundant system of sums of products (SoPs) describing the behavior of the correct circuit have been developed. The algorithm appreciating the size of the unprotected area is also given

Le fonds grec de la Bibliothèque nationale.

Omont Henri. Le fonds grec de la Bibliothèque nationale.. In: Bibliothèque de l'école des chartes. 1883, tome 44. pp. 569-572