Implementación de un controlador borroso usando técnicas de PWM analógico

Hoy día la mayoría de los sistemas de control borroso se implementan en software usando procesadores y micro controladores digitales. Los diseños digitales programables son capaces de resolver muchos problemas de control, pero en sistemas de tiempo real, donde las señales de control tienen que cambiar en solo unos ciclos del reloj, la implementación hardware es la única solución posible. En este artículo se presenta un diseño de VLSI hardware, basado en técnicas de diseño analógicas usando trenes de pulsos. El diseño implementa todas las partes de un controlador borroso de alta velocidad. Se ha construido un chip de prueba en 1.5um CMOS

Revealing hidden scenes by photon-efficient occlusion-based opportunistic active imaging

The ability to see around corners, i.e., recover details of a hidden scene from its reflections in the surrounding environment, is of considerable interest in a wide range of applications. However, the diffuse nature of light reflected from typical surfaces leads to mixing of spatial information in the collected light, precluding useful scene reconstruction. Here, we employ a computational imaging technique that opportunistically exploits the presence of occluding objects, which obstruct probe-light propagation in the hidden scene, to undo the mixing and greatly improve scene recovery. Importantly, our technique obviates the need for the ultrafast time-of-flight measurements employed by most previous approaches to hidden-scene imaging. Moreover, it does so in a photon-efficient manner based on an accurate forward model and a computational algorithm that, together, respect the physics of three-bounce light propagation and single-photon detection. Using our methodology, we demonstrate reconstruction of hidden-surface reflectivity patterns in a meter-scale environment from non-time-resolved measurements. Ultimately, our technique represents an instance of a rich and promising new imaging modality with important potential implications for imaging science.Comment: Related theory in arXiv:1711.0629

Improving the design process of VLSI circuits by means of a hardware debugging system: UNSHADES-1 framework

Due to the increase in size and complexity of VLSI integrated circuits, new design tools are becoming needed. Telecommunications and Electronic Industry demand designs that integrate intensive digital signal processing blocks and complex control tasks. Rapid Prototyping techniques introduce a new stage into the design flow that overcome the drawbacks of simulation stage and shorten design times. Advanced FPGAs can host the design for its emulation and can run inserted into the final system. The benefits of their use go beyond the simple rapid prototyping approach, and are able to provide additional information and other useful tasks that will be presented in this paper

HADES-1: A rapid prototyping environment based on advanced FPGA’s

Rapid prototyping of large digital systems is becoming supported with the use of new advanced FPGA's. These FPGA's can give more Information than functional simulation and emulation tasks, due to their inner inspection features. This paper presents HADES-l, a new environment for rapid prototyping and hardware debugging. HADES-l is based on one FPGA of the VIRTEX family, exploiting the advanced features of the SelectMap port and a fast link with the host PC

ASIC-based tachometer without mechanical transducer for induction machines

A classical method for angular position and speed estimation in adjustable speed drives uses an incremental shaft encoder and an electronic circuit. This paper presents SLESS, a tachometer without mechanical transducer implemented on an ASIC using sensorless speed estimation technique. The ASIC is intended to serve as part of an integrated solution developed for fuzzy speed regulation and vector control of induction motors

ASITRON: ASIC for indirect vector control of induction motors with fuzzy logic based speed regulation

This paper presents ASITRON, an integrated solution for the vector control of induction motors. This ASIC is a micro-system that integrates, in a chip, all the logic required by the indirect vector control method. ASITRON implements a PWM based current control loop, the measure of speed based on a biphase pulse signal encoder, a fuzzy logic based speed and position outer control loop and a microprocessor external parallel interface. A built-in 64-rules fuzzy logic controller can be programmed to deal with the speed or position outer control loop. This integrated solution is the essential part of a compact, high performance, industrial control system for elevators

Design of a band-pass sigma-delta modulator with reduced number of opamps

This paper is intended to compare the performance of a Band-Pass converter structure and its Low-Pass prototype 2nd order Sigma-Delta Analog to Digital converter. For this purpose Matlab simulations for the 4th order Band-Pass converter have been performed and its power consumption calculated when using the equivalent Op-Amp used m the Low-Pass modulator. First of all will be described the method used to calculate the transfer function and, thus the structure of the Band-Pass structure to be tested. After a band-pass transfer function has been obtained it is implemented using reduced number of opamps. This topology is compared to the existing ones and a system level simulation and characterisation is performed. Finally, jitter limitations are studied. Transistor level simulations using Spectre have been done in order to validate MATLAB simulations prior to layout design

Integrated solution for induction motor control

The command speed has an 'S' shape, typical in vertical operation systems. The reason for this command speed is that a soft acceleration/deceleration avoids abrupt movements in the elevator cabin, increasing the comfort level. A Fuzzy-logic based controller for the speed and position control based on an ASIC design

Microprocessor and FPGA interfaces for in-system co-debugging in field programmable hybrid systems

Modern trends in technology require efficient control and processing platforms based on connected software-hardware subsystems. Due to their complexity and size, algorithms implemented on these platforms are difficult to test and verify. When these types of solution are being designed, it is necessary to provide information of the internal values of registers and memories of both the software and hardware during the execution of the complete system. The final architecture of the targeted design and its debugging capabilities strongly depends on how the hybrid system is connected and clocked. This article discusses different architectural strategies that have been adopted for a hybrid hardware-software platform, built ready for debugging, and that uses components that can be easily found with a few special features. All the solutions have been implemented and evaluated using the UNSHADES-2 framework

Modelling search for people in 900 scenes: A combined source model of eye guidance

How predictable are human eye movements during search in real world scenes? We recorded 14 observers’ eye movements as they performed a search task (person detection) in 912 outdoor scenes. Observers were highly consistent in the regions fixated during search, even when the target was absent from the scene. These eye movements were used to evaluate computational models of search guidance from three sources: Saliency, target features, and scene context. Each of these models independently outperformed a cross-image control in predicting human fixations. Models that combined sources of guidance ultimately predicted 94% of human agreement, with the scene context component providing the most explanatory power. None of the models, however, could reach the precision and fidelity of an attentional map defined by human fixations. This work puts forth a benchmark for computational models of search in real world scenes. Further improvements in modelling should capture mechanisms underlying the selectivity of observers’ fixations during search.National Eye Institute (Integrative Training Program in Vision grant T32 EY013935)Massachusetts Institute of Technology (Singleton Graduate Research Fellowship)National Science Foundation (U.S.) (Graduate Research Fellowship)National Science Foundation (U.S.) (CAREER Award (0546262))National Science Foundation (U.S.) (NSF contract (0705677))National Science Foundation (U.S.) (Career Award (0747120)