Technology Scaling Impact on Embedded ADC Design for Telecom Receivers

This paper is concerned with the impact of technology scaling on the choice of A/D converters in telecom receivers. It is shown that the trend of diminishing feature size, together with better matching of passive components, allows the use of A/D topologies traditionally confined to low-frequency, medium-resolution applications. The design of a 10 bit 20 MS/s ADC using the successive approximation algorithm is presented in order to validate the presented concepts. By using a deep-submicron technology, the speed of the chosen architecture is pushed to meet the desired output rate

A fast and low noise charge sensitive preamplifier in 90 nm CMOS technology

A fast charge sensitive preamplifier was designed and built in a 90 nm CMOS technology. The work is part of the R&D effort towards the read out of pixel or small strip sensors in next generation HEP experiments. The preamplifier features outstanding noise performance given its wide bandwidth, with a ENC (equivalent noise charge) of about 350 electrons RMS with a detector of 1 pF capacitance. With proper filtering, the ENC drops to less than 200 electrons RMS. Power consumption is 5 mW for one channel, and the closed loop bandwith is about 180 MHz, for a risetime down to 2 ns in the fastest operation mode. Thanks to some freedom left to the user in setting the open loop gain, detectors with larger source capacitance can be read out without significant loss in bandwidth, being the rise time still 5.5 ns for a 5.6 pF detector. The output can drive a 50 Ω terminated transmission line. © 2012 2012 IOP Publishing Ltd and SISSA

Low-voltage fully-differential switched-opamp bandpass ΣΔ modulator

The paper deals with the design of a low-voltage bandpass ΣΔ modulator implemented with the switched-capacitor technique. To use standard technology (no low-threshold devices) and without an on-chip voltage multiplier, the switched-opamp technique has been adopted. The basic building blocks for the construction of a ΣΔ modulator (SC integrator, quantiser, and feedback DAC) are proposed in a fully differential version. In addition, they have been improved with respect to those previously reported to give a larger output swing at a higher sampling frequency and without any voltage reference. The validity of the proposed circuits is demonstrated by the realisation of a second-order bandpass ΣΔ modulator operating with a single 1 V supply within a standard 0.5 μm CMOS technology (VTHn=0.65 V, VTHp=0.7 V). The modulator operates at a sampling frequency of 1.8 MHz with a full-scale input range of 2 Vpk-pk and achieves a 45 dB dynamic range in a 20 kHz bandwidt

The Evolution of Integrated Interfaces for MEMS Microphones

Over the last decade, MEMS microphones have become the leading solution for implementing the audio module in most portable devices. One of the main drivers for the success of the MEMS microphone has been the continuous improvement of the corresponding integrated interface circuit performance in terms of both dynamic range and power consumption, which enabled the introduction in mobile devices of additional functionalities, such as Hi-Fi audio recording or voice commands. As a result, MEMS microphone interface circuits evolved from just simple amplification stages to complex mixed-signal circuits, including A/D converters, with ever improving performance. This paper provides an overview of such evolution based on actual design examples, focusing, finally, on the latest cutting-edge solutions