Uncovering of major genetic factors generating naturally occurring variation in heading date among Asian rice cultivars

To dissect the genetic factors controlling naturally occurring variation of heading date in Asian rice cultivars, we performed QTL analyses using F2 populations derived from crosses between a japonica cultivar, Koshihikari, and each of 12 cultivars originating from various regions in Asia. These 12 diverse cultivars varied in heading date under natural field conditions in Tsukuba, Japan. Transgressive segregation was observed in 10 F2 combinations. QTL analyses using multiple crosses revealed a comprehensive series of loci involved in natural variation in flowering time. One to four QTLs were detected in each cross combination, and some QTLs were shared among combinations. The chromosomal locations of these QTLs corresponded well with those detected in other studies. The allelic effects of the QTLs varied among the cross combinations. Sequence analysis of several previously cloned genes controlling heading date, including Hd1, Hd3a, Hd6, RFT1, and Ghd7, identified several functional polymorphisms, indicating that allelic variation at these loci probably contributes to variation in heading date. Taken together, the QTL and sequencing results indicate that a large portion of the phenotypic variation in heading date in Asian rice cultivars could be generated by combinations of different alleles (possibly both loss- and gain-of-function) of the QTLs detected in this study

Parallel Real-Time PCR on a Chip for Genetic Tug-of-War (gTOW) Method

A microchip-based real-time polymerase chain reaction (PCR) device has been developed for the genetic tug-of-war (gTOW) method that provides quantitative data for research on biorobustness and systems biology. The device was constructed of a silicon glass chip, a temperature controlling Peltier element, and a microscope. A parallel real-time amplification process of target genes on the plasmids and the housekeeping genes in a model eukaryote Saccharomyces cerevisiae were detected simultaneously, and the copy number of the target genes were estimated. The device provides unique quantitative data that can be used to augment understanding of the system-level properties of living cells

Monolithic CMOS sensors for sub-nanosecond timing

In the ATTRACT project FASTPIX we investigate monolithic pixel sensors with small collection electrodes in CMOS technologies for fast signal collection and precise timing in the sub-nanosecond range. Deep submicron CMOS technologies allow tiny, sub-femtofarad collection electrodes, and large signal-to-noise ratios, essential for very precise timing. However, complex in-pixel circuits require some area, and one ofthe key limitations for precise timing is the longer drift time of signal charge generated near the pixel borders.Laying out the collection electrodes on a hexagonal grid and reducing the pixel pitch minimize the maximumdistance from the pixel border to the collection electrode. The electric field optimized with TCAD simulationspulls the signal charge away from the pixel border towards the collection electrode as fast as possible. Thisalso reduces charge sharing and maximizes the seed pixel signal hence reducing time-walk effects. Here thehexagonal geometry also contributes by limiting charge sharing at the pixel corners to only three pixels insteadof four. We reach pixel pitches down to about 8.7 μmbetween collection electrodes in this 180 nm technologyby placing only a minimum amount of circuitry in the pixel and the rest at the matrix periphery. Consumingseveral tens of micro-ampere per pixel from a 1.8 V supply offers a time jitter of only a few tens of picoseconds.This allows detailed characterization of the sensor timing performance in a prototype chip with several minimatrices of 64 pixels each with amplifier, comparator and digital readout and 4 additional pixels with analogbuffers. The aim is to prove sensor concepts before moving to a much finer line width technology and fullyintegrate the readout within the pixel at lower power consumption

A Pixel Design of a Branching Ultra-Highspeed Image Sensor

A burst image sensor named Hanabi, meaning fireworks in Japanese, includes a branching CCD and multiple CMOS readout circuits. The sensor is backside-illuminated with a light/charge guide pipe to minimize the temporal resolution by suppressing the horizontal motion of signal carriers. On the front side, the pixel has a guide gate at the center, branching to six first-branching gates, each bifurcating to second-branching gates, and finally connected to 12 (=6×2) floating diffusions. The signals are either read out after an image capture operation to replay 12 to 48 consecutive images, or continuously transferred to a memory chip stacked on the front side of the sensor chip and converted to digital signals. A CCD burst image sensor enables a noiseless signal transfer from a photodiode to the in-situ storage even at very high frame rates. However, the pixel count conflicts with the frame count due to the large pixel size for the relatively large in-pixel CCD memory elements. A CMOS burst image sensor can use small trench-type capacitors for memory elements, instead of CCD channels. However, the transfer noise from a floating diffusion to the memory element increases in proportion to the square root of the frame rate. The Hanabi chip overcomes the compromise between these pros and cons