Experimental and Numerical Study of Motion Chracteristics of An Equi-Hull Trimaran

Source: ICHE Conference Archive - https://mdi-de.baw.de/icheArchiv

Hardware in the Loop Simulation and Control Design for Autonomous Free Running Ship Models

This paper presents an hardware-in-the-loop (HIL) simulation system tool to test and validate an autonomous free running model system for ship hydrodynamic studies with a view to verification of the code, the control logic and system peripherals. The computer simulation of the plant model in real-time computer does not require the actual physical system and reduces the development cost and time for control design and testing purposes. The HIL system includes: the actual programmable embedded controller along with peripherals and a plant model virtually simulated in a real-time computer. With regard to ship controller design for ship model testing, this study describes a plant model for surge and a Nomoto first order steering dynamics, both implemented using Simulink software suit. The surge model captures a quasi-steady state relationship between surge speed and the propeller rpms, obtained from simple forward speed towing tank tests or derived analytically. The Nomoto first order steering dynamics is obtained by performing the standard turning circle test at model scale. The control logic obtained is embedded in a NI-cRIO based controller. The surge and steering dynamics models are used to design a proportional-derivative controller and an LQR controller. The controller runs a Linux based real-time operating system programmed using LabVIEW software. The HIL simulation tool allows for the emulation of standard ship hydrodynamic tests consisting of straight line, turning circle and zigzag to validate the combined system performance, prior to actual for use in the autonomous free-running tests

Role of Elasticity on Forces and Deflections of a Submerged Elastic Plate in Waves

Source: ICHE Conference Archive - https://mdi-de.baw.de/icheArchiv

A router architecture for QoS capable clusters

Interconnection Networks have been used as a high performance communication fabric in parallel processor architectures. Parallel processors built using off-the-shelf components, called clusters, are becoming increasingly attractive because of their high performance to cost ratio over parallel computers. Many web servers and database servers make efficient use of clustering from cost, scalability and availability standpoints. The Design of high performance cluster networks with QoS guarantees is becoming increasingly important to support a variety of multimedia applications, many of which have real time constraints. Most commercial routers, which are based on the wormhole switching paradigm, can deliver high performance, but lack QoS provisioning. A new router architecture with support for QoS provisioning was introduced in [1]. In this project we present a detailed analysis of the hardware complexity of the router in [1] and propose some architectural modifications to reduce the hardware complexity of the router. We have also developed a simulator to compare and analyze the performance characteristics of the proposed router architecture

Energy Conservation Method Combining Anti spray Rail and Wedge Flap for High speed Displacement Hulls

The hydrodynamic mechanism and parametric influences of the wedge flap and the anti-spray rail in combination is investigates. A methodology with specific guidelines for incorporating these appendages with significant drag reduction is provided. Small crafts designs frequently require interventional changes to realise the desired guaranteed speed with their installed engine power. The appendages namely, the wedge, flap and anti-spray rails are used as retrofit measures or adapted in new hull forms, in isolation or in combination, to improve the drag and bring down the power requirement. A judicious combination of different appendages can result in significantly reduced drag and therefore power saving. The methodology combines the results of numerical and experimental investigations. The systematic study identifies the parameters for control namely, wedge flap size in terms of the chord length, its orientation vide the angle of the wedge flap, and the anti-spray rail location with respect to the water surface. The choice of the size of the wedge flap is a constrained problem since excessive wedge flap can cause problems related to length and hydrodynamic loading. This study establishes a solution by combination of a minimum integrated wedge flap with properly located anti-spray rail to reduce the drag. The study shows favourable influences due to local pressure and numerical results using a RANSE solver show good comparison with experimental test results. The methodology is a new approach towards drag reduction in new designs as well as drag control by retrofit

SMART: A Single-Cycle Reconfigurable NoC for SoC Applications

As technology scales, SoCs are increasing in core counts, leading to the need for scalable NoCs to interconnect the multiple cores on the chip. Given aggressive SoC design targets, NoCs have to deliver low latency, high bandwidth, at low power and area overheads. In this paper, we propose Single-cycle Multi-hop Asynchronous Repeated Traversal (SMART) NoC, a NoC that reconfigures and tailors a generic mesh topology for SoC applications at runtime. The heart of our SMART NoC is a novel low-swing clockless repeated link circuit embedded within the router crossbars, that allows packets to potentially bypass all the way from source to destination core within a single clock cycle, without being latched at any intermediate router. Our clockless repeater link has been proven in silicon in 45nm SOI. Results show that at 2GHz, we can traverse 8mm within a single cycle, i.e. 8 hops with 1mm cores. We implement the SMART NoC to layout and show that SMART NoC gives 60% latency savings, and 2.2X power savings compared to a baseline mesh NoC.United States. Defense Advanced Research Projects Agency. The Ubiquitous High-Performance Computing Progra

Fin based active control for ship roll motion stabilization

Ship roll motion control is important for vessels engaged in oceanographic research activities and this paper focuses on the design of a controller for fin based roll motion stabilization of a Coastal Research Vessel (CRV). Based on the geometry of a pair of actuator fins installed at the midship of the vessel, the hydrodynamic coefficients are calculated for the vessel including the fin lift capacity. The wave disturbances are simulated as a sine time series. The objective is to design a Linear Quadratic Regulator (LQR), a state feedback controller and obtain the performance of the system. The larger objective is to implement the system eventually in laboratory scale physical simulations in wave environment. This paper primarily presents the design of the control system and evaluation through Simulink in Matlab environment. The global cost function of the system is minimized by precision tuning of the two control parameters (or weighting matrices), Q and R. The system analysis is done using frequency domain and state space approach. The simulation results show that the natural frequency and roll response closely match with the response of the physical model (CRV) in laboratory environment, as observed during the experimental study. The proposed control system is compared with a conventional PID controller. The simulation results demonstrate the effectiveness of the designed roll motion stabilization system with significant roll reduction over the operational range of the vessel

SCORPIO: A 36-Core Research Chip Demonstrating Snoopy Coherence on a Scalable Mesh NoC with In-Network Ordering

URL to conference programIn the many-core era, scalable coherence and on-chip interconnects are crucial for shared memory processors. While snoopy coherence is common in small multicore systems, directory-based coherence is the de facto choice for scalability to many cores, as snoopy relies on ordered interconnects which do not scale. However, directory-based coherence does not scale beyond tens of cores due to excessive directory area overhead or inaccurate sharer tracking. Prior techniques supporting ordering on arbitrary unordered networks are impractical for full multicore chip designs. We present SCORPIO, an ordered mesh Network-on-Chip(NoC) architecture with a separate fixed-latency, bufferless network to achieve distributed global ordering. Message delivery is decoupled from the ordering, allowing messages to arrive in any order and at any time, and still be correctly ordered. The architecture is designed to plug-and-play with existing multicore IP and with practicality, timing, area, and power as top concerns. Full-system 36 and 64-core simulations on SPLASH-2 and PARSEC benchmarks show an average application run time reduction of 24.1% and 12.9%, in comparison to distributed directory and AMD HyperTransport coherence protocols, respectively. The SCORPIO architecture is incorporated in an 11 mm-by- 13 mm chip prototype, fabricated in IBM 45nm SOI technology, comprising 36 Freescale e200 Power Architecture TM cores with private L1 and L2 caches interfacing with the NoC via ARM AMBA, along with two Cadence on-chip DDR2 controllers. The chip prototype achieves a post synthesis operating frequency of 1 GHz (833 MHz post-layout) with an estimated power of 28.8 W (768 mW per tile), while the network consumes only 10% of tile area and 19 % of tile power.United States. Defense Advanced Research Projects Agency (DARPA UHPC grant at MIT (Angstrom))Center for Future Architectures ResearchMicroelectronics Advanced Research Corporation (MARCO)Semiconductor Research Corporatio

Energy conserving broadcast routing in mobile ad hoc networks

In this thesis, we consider the problem of broadcast routing in a wireless ad hoc network from the viewpoint of energy efficiency. Each node in a wireless ad hoc network runs on a local energy source, which has a very limited energy life span. Thus, energy conservation is a critical issue in such networks.Master of Science (Communication Software and Networks