Performance Analysis of Montgomery Multiplier using 32nm CNTFET Technology

In VLSI design vacillating the parameters results in variation of critical factors like area, power and delay. The dominant sources of power dissipation in digital systems are the digital multipliers. A digital multiplier plays a major role in a mixture of arithmetic operations in digital signal processing applications hinge on add and shift algorithms. In order to accomplish high execution speed, parallel array multipliers are comprehensively put into application. The crucial drawback of these multipliers is that it exhausts more power than any other multiplier architectures. Montgomery Multiplication is the popularly used algorithm as it is the most efficient technique to perform arithmetic based calculations. A high-speed multiplier is greatly coveted for its extraordinary leverage. The primary blocks of a multiplier are basically comprised of adders. Thus, in order to attain a significant reduction in power consumption at the chip level the power utilization in adders can be decreased. To obtain desired results in performance parameters of the multiplier an efficient and dynamic adder is proposed and incorporated in the Montgomery multiplier. The Carbon Nanotube field effect transistor (CNTFET) is a promising new device that may supersede some of the fundamental limitations of a silicon based MOSFET. The architecture has been designed in 130nm and 32nm CMOS and CNTFET technology in Synopsys HSpice. The analysed parameters that are considered in determining the performance are power delay product, power and delay and comparison is made with both the technologies.The simulation results of this paper affirmed the CNTFET based Montgomery multiplier improved power consumption by 76.47% ,speed by 72.67% and overall energy by 67.76% as compared to MOSFET-based Montgomery multiplier

Optimization of high-k composite dielectric materials of variable oxide thickness tunnel barrier for nonvolatile memory

Downscaling the tunnel oxide thickness has become one of the innovative solutions to minimize the operational voltage with better the programming/erasing (P/E) operation time. However, the downscaling technique faces several challenges where the conventional SiO2 tunnel layer has reached its limit. But a practical alternative has been introduced; Variable Oxide Thickness (VARIOT) technology in flash memory has been promising. VARIOT is one of tunnel barrier engineering technology for incorporating the high-k dielectric materials as a composite tunnel barrier. This paper presents the VARIOT concept to determine the optimum set of combination, the equivalent oxide thickness (EOT) and the low-k oxide thickness (Tox) for alternate high-k materials. Fowler-Nordheim (F-N) tunneling coefficients are also extracted for various combinations of VARIOT, where in this work ZrO2, HfO2, Al2O3, La2O3, and Y2O3 are used. The VARIOT optimization is conducted using 3-Dimensional (3D) Silicon Nanowire Field-Effect-Transistor (SiNWFET) device structure and simulated in TCAD Simulation tools. From the simulation results, it has found out that the high-k materials of La2O3 asymmetric stack is the excellent dielectric material among four (4) other dielectric materials; ZrO2, HfO2, Al2O3 and Y2O3 for EOT=4nm and Tox=1nm

Temperature Variation Operation of Mixed-VT 3T GC-eDRAM for Low Power Applications in 2Kbit Memory Array

Embedded memories were once utilized to transfer information between the CPU and the main memory. The cache storage in most traditional computers was static-random-access-memory (SRAM). Other memory technologies, such as embedded dynamic random-access memory (eDRAM) and spin-transfer-torque random-access memory (STT-RAM), have also been used to store cache data. The SRAM, on the other hand, has a low density and severe leakage issues, and the STT-RAM has high latency and energy consumption when writing. The gain-cell eDRAM (GC-eDRAM), which has a higher density, lower leakage, logic compatibility, and is appropriate for two-port operations, is an attractive option. To speed up data retrieval from the main memory, future processors will require larger and faster-embedded memories. Area overhead, power overhead, and speed performance are all issues with the existing architecture. A unique mixed-V_T 3T GC-eDRAM architecture is suggested in this paper to improve data retention times (DRT) and performance for better energy efficiency in embedded memories. The GC-eDRAM is simulated using a standard complementary-metal-oxide-semiconductor (CMOS) with a 130nm technology node transistor. The performance of a 2kbit mixed-V_T 3T GC-eDRAM array were evaluated through corner process simulations. Each memory block is designed and simulated using Mentor Graphics Software. The array, which is based on the suggested bit-cell, has been successfully operated at 400Mhz under a 1V supply and takes up almost 60-75% less space than 6T SRAM using the same technology. When compared to the existing 6T and 4T ULP SRAMs (others' work), the retention power of the proposed GC-eDRAM is around 80-90% lower

Reliability of graphene as charge storage layer in floating gate flash memory

This study aims to investigate the memory performances of graphene as a charge storage layer in the floating gate with difference doping concentration of n-channel and p-channel substrates using Silvaco ATLAS TCAD Tools. The simulation work has been done to determine the performance of flash memory in terms of memory window, P/E characteristics and data retention and have been validated with the experimental work done by other researchers. From the simulation data, the trend of memory window at low P/E voltage is nearly overlapped between simulation and experimental data. The memory window at ±20V P/E voltage for n-channel and p-channel flash memory cell are 15.4V and 15.6V respectively. The data retention for the n-channel flash memory cell is retained by 75% (from 15.4V to 11.6V) whereas for the p-channel flash memory cell is retained by 80% (from 15.6V to 12.5V) after 10 years of extrapolation with -1/1V gate stress which shows that p-channel flash memory cell demonstrates better data retention compared to n-channel flash memory cell

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/ high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/ Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of %3.6/3.6V gate stress

Adsorption site of gas molecules on defective armchair graphene nanoribbon formed through ion bombardment

High sensitivity and selectivity is desired in sensing devices. The aim of this study is to investigate the use of the ion bombardment process in creating a defect on graphene nanoribbons (GNR), which significantly affects sensing properties, in particular adsorption energy, charge transfer and sensitivity. A process has been developed to form the defect on the GNR surface using molecular dynamic (MD) with a reactive force field with nitrogen ion. The sensing properties were calculated using the extended Huckel theory when oxygen (O2) and ammonia (NH3) molecules are exposed to different areas on the defective site. Through simulation, it was found that the ion bombardment process formed various types of defects on the GNR surface. Most notably, molecules adsorbed on the ripple area considerably improve the sensitivity by more than 50%. This indicates that the defect on the armchair graphene nanoribbon (AGNR) surface can be a method to enhance graphene-based sensing performance

Explicit continuous models of drain current, terminal charges and intrinsic capacitance for a long-channel junctionless nanowire transistor

An explicit charge-based solution for the drain current, terminal charges and intrinsic capacitance of a long-channel junctionless nanowire transistor (JNT) incorporating the importance of an interface trap density that affect the threshold voltage and the subthreshold slope is presented in this study. Initially, a continuous implicit solution of the unified charge-based control model (UCCM) is derived from the 1D Poisson equation by invoking the parabolic potential approximation. The the continuous solution of the mobile charge density at the source/drain is obtained by adding the decoupled UCCM expression for the depletion and complementary parts, where each part is explicitly solved using the Lambert function without having an additional smoothing function to unify the two limits. The omission of an additional smoothing function could lead to a shorter computation time. Secondly, by solving Pao-Sah's dual integral, a continuous charge-based expression for the drain current is derived. The expressions for the terminal charge are then derived based on the decoupled drain current model that also becomes an input for computing all four independent capacitances of the JNT. The explicit continuous models show a good agreement with numerical simulation over practical terminal voltages, doping levels, and geometry effects. For a given maximum surface potential error of 5%, the model is accurate for a dopant-geometry ratio of 0.001 < qN D R 2/4 Si < 0.3 and it is also independent of fitting parameters that may vary for different terminal biases or dopant geometries. The nonpiecewise models for drain current, terminal charges and intrinsic capacitance are significantly resolved by decoupling the mobile charge into depletion and complementary parts with no additional smoothing function to unify between operating regions, and omitting fitting parameters that have no physical meaning

Performance analysis of junctionless multi-bridge channel FET with strained SiGe application

In this work, a 12 nm 3-Dimensional (3D) strained Junctionless (JL) Multi-Bridge Channel Field Effect Transistor (MBCFET) with different Germanium (Ge) mole fractions from 0.1 to 0.4 are presented. The strain used in this work is Silicon-Germanium (SiGe) which is applied in between the channels of MBCFET. The electrical performances such as on-current, threshold voltage and potential distributions along the channel are conducted by using the Silvaco TCAD simulator. It was found that the strained JL MBCFET performs better compared to unstrained JL MBCFET. The results show that by inducing strain on JL MBCFET, the on-current increased by 29%, threshold voltage shifted by 0.25 V and potential in the centre of the channel was reduced by 13 %

Comprehensive analysis of gate oxide short in junctionless fin field effect transistor

Junctionless (JL) FinFET is one of the most promising alternatives to FinFET and planar MOSFET for future performance enhancements. The complexity of the JL FinFET manufacturing process has prompted difficulties in reliable device testing. Gate oxide short (GOS) is one of the most common faults that substantially influence circuit reliability, specifically in FinFET device structure. In this work, GOS defect model is presented for both n-channel and p-channel JL FinFET and JL FinFET-based inverter by introducing the defect as a pinhole designated by small cuboid cuts of different sizes for several coordination in the dielectric and filled with gate material. The electrical characteristics of 15nm n- and p-channel JL FinFET with fin height and width of 10nm, source/drain, channel and substrate doping concentration of 1.5×1019 cm-3, and work function of 4.76eV and 4.52eV for n- and p-channel are successfully simulated by using Synopsys Sentaurus TCAD Tools where Vth, SS, and DIBL are 0.371V, 75.7mV/dec and 42.7mV for n-channel and 0.3298V, 79.1mV/dec and 48.9mV for p-channel JL FinFET respectively that is compared with post GOS defect injection. The high-to-low delay time (tHL) is 1.61ps and low-to-high delay time (tLH) is 1.74ps for the defect-free inverter that is compared to the defected one where the tHL is 16.1 % and tLH is 22.4 % smaller than defective inverter. The findings of this research potentially result in the formation of a realistic analytical GOS fault model for circuit-level modeling