8 research outputs found
Flip chip packaging of digital silicon photonics MEMS Switch for cloud computing and data centre
We report on the flip chip packaging of Micro-Electro-Mechanical System (MEMS)-based digital silicon photonic switching device and the characterization results of 12 × 12 switching ports. The challenges in packaging N2 electrical and 2N optical interconnections are addressed with single-layer electrical redistribution lines of 25 µm line width and space on aluminum nitride interposer and 13° polished 64-channel lidless fiber array (FA) with a pitch of 127 µm. 50 µm diameter solder spheres are laser-jetted onto the electrical bond pads surrounded by suspended MEMS actuators on the device before fluxless flip-chip bonding. A lidless FA is finally coupled near-vertically onto the device gratings using a 6-degree-of-freedom (6-DOF) alignment system. Fiber-to-grating coupler loss of 4.25 dB/facet, 10–11 bit error rate (BER) through the longest optical path, and 0.4 µs switch reconfiguration time have been demonstrated using 10 Gb/s Ethernet data stream
Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant
We introduce an approach to designing FPGA-accelerated middleboxes that
simplifies development, debugging, and performance tuning by decoupling the
tasks of hardware-accelerator implementation and software-application
programming. Rosebud is a framework that links hardware accelerators to a
high-performance packet processing pipeline through a standardized
hardware/software interface. This separation of concerns allows hardware
developers to focus on optimizing custom accelerators while freeing software
programmers to reuse, configure, and debug accelerators in a fashion akin to
software libraries. We show the benefits of the Rosebud framework by building a
firewall based on a large blacklist and porting the Pigasus IDS
pattern-matching accelerator in less than a month. Our experiments demonstrate
that Rosebud delivers high performance, serving ~200 Gbps of traffic while
adding only 0.7-7 microseconds of latency.Comment: 20 pages. Final version, to appear in ASPLOS2
Integrating Microsecond Circuit Switching into the Data Center
Recent proposals have employed optical circuit switching (OCS) to reduce the cost of data center networks. However, the relatively slow switching times (10–100 ms) assumed by these approaches, and the accompanying latencies of their control planes, has limited its use to only the largest data center networks with highly aggregated and constrained workloads. As faster switch technologies become available, designing a control plane capable of supporting them becomes a key challenge. In this paper, we design and implement an OCS prototype capable of switching in 11.5 µs, and we use this prototype to expose a set of challenges that arise when supporting switching at microsecond time scales. In response, we propose a microsecond-latency control plane based on a circuit scheduling approach we call Traffic Matrix Scheduling (TMS) that proactively communicates circuit assignments to communicating entities so that circuit bandwidth can be used efficiently