ECG signal denoising using a novel approach of adaptive filters for real-time processing

Electrocardiogram (ECG) is considered as the main signal that can be used to diagnose different kinds of diseases related to human heart. During the recording process, it is usually contaminated with different kinds of noise which includes power-line interference, baseline wandering and muscle contraction. In order to clean the ECG signal, several noise removal techniques have been used such as adaptive filters, empirical mode decomposition, Hilbert-Huang transform, wavelet-based algorithm, discrete wavelet transforms, modulus maxima of wavelet transform, patch based method, and many more. Unfortunately, all the presented methods cannot be used for online processing since it takes long time to clean the ECG signal. The current research presents a unique method for ECG denoising using a novel approach of adaptive filters. The suggested method was tested by using a simulated signal using MATLAB software under different scenarios. Instead of using a reference signal for ECG signal denoising, the presented model uses a unite delay and the primary ECG signal itself. Least mean square (LMS), normalized least mean square (NLMS), and Leaky LMS were used as adaptation algorithms in this paper

A reduced size look up table for sinusoidal wave generation in digital modulators applications

Digital Modulators is one of the areas that have received great attention recently due to the tremendous developments in Radio Frequency (RF) frond ends and system on chips (soc) architecture in general. Building any kind of digital modulators using soc type Field Programmable Gate Array (FPGA), like ZYBO, depends heavily on how the carrier signal got generated since it consumes a lot of utilization recourses. This paper presents a new method of generating sinusoidal carrier signal based on Direct Digital Synthesizer (DDS) concept using small size Look Up Table (LUT). 64 samples of a quarter period of the sine wave signal were stored in a fixed point format in small LUT to generate the carrier at the desire frequency. The paper used Very high speed integrated circuit Hardware Descriptive Language (VHDL) without the help of DSP Builder Tools or XILINX System Generator. The suggested method was tested by building simple modulators like On-Off Keying (OOK) and Amplitude Shift Keying (ASK). Low utilization was achieved as compared to other implementation methods